Solid-state imaging device

Patent metadata

Field	Value
Publication number	US-12136640-B2
Application number	US-202017620228-A
Country	US
Kind code	B2
Filing date	Jun 26, 2020
Priority date	Jun 26, 2019
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.

First claim

What is claimed is:

1. A solid-state imaging device, comprising:
a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, wherein the electric charge accumulation section accumulates a signal electric charge generated in the photoelectric converter;
a pixel separation section that is provided in the first semiconductor layer, wherein the pixel separation section partitions a plurality of the pixels from each other;
a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, wherein the pixel transistor reads the signal electric charge of the electric charge accumulation section; and
a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, wherein the first shared coupling section straddles the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections;
a first substrate including the first semiconductor layer and a first wiring layer provided with the first shared coupling section;
a second substrate including the second semiconductor layer and a second wiring layer that is opposed to the first substrate with the second semiconductor layer interposed therebetween;
a third substrate that is opposed to the first substrate with the second substrate interposed therebetween, and includes a circuit that is electrically coupled to the second semiconductor layer; and
a first through electrode that electrically couples the first shared coupling section and the pixel transistor to each other, and is provided in the first substrate and the second substrate.

2. The solid-state imaging device according to claim 1 , wherein the first shared coupling section includes polysilicon.

3. The solid-state imaging device according to claim 1 , wherein the electric charge accumulation section includes arsenic.

4. The solid-state imaging device according to claim 1 , wherein the first shared coupling section includes polysilicon and has an alloy region that is partially alloyed, and the first through electrode is coupled to the alloy region.

5. The solid-state imaging device according to claim 1 , wherein
the first semiconductor layer further includes a transfer transistor that includes a gate electrode opposed to the first semiconductor layer, and transfers the signal electric charge of the photoelectric converter to the electric charge accumulation section, and the transfer transistor and the pixel transistor have shapes different from each other.

6. The solid-state imaging device according to claim 5 , wherein gate electrodes of the transfer transistor and the pixel transistor are covered with respective sidewalls having widths different from each other.

7. The solid-state imaging device according to claim 5 , wherein gate electrodes of the transfer transistor and the pixel transistor have heights different from each other.

8. The solid-state imaging device according to claim 1 , wherein
the second semiconductor layer includes, as the pixel transistor, an amplification transistor, a selection transistor, a reset transistor, and an FD conversion gain switching transistor, and
the amplification transistor, the selection transistor, the reset transistor, and the FD conversion gain switching transistor each have a planar structure or a three-dimensional structure.

9. The solid-state imaging device according to claim 1 , further comprising:
an impurity diffusion region that is provided in the first semiconductor layer for each of the pixels, and is disposed apart from the electric charge accumulation section;
a second shared coupling section that is provided in the first wiring layer, wherein the second shared coupling section straddles the pixel separation section and is electrically coupled to a plurality of the impurity diffusion regions; and
a second through electrode that electrically couples the second shared coupling section and a predetermined region of the second semiconductor layer to each other, wherein the second through electrode is provided in the first substrate and the second substrate.

10. The solid-state imaging device according to claim 1 , further comprising:
a transfer transistor that includes a gate electrode opposed to the first semiconductor layer, wherein the transfer transistor transfers the signal electric charge of the photoelectric converter to the electric charge accumulation section; and
a third through electrode that is electrically coupled to a gate of the transfer transistor, wherein the third through electrode is provided for each of the plurality of pixels each including a corresponding one of a plurality of the electric charge accumulation sections that is electrically coupled to each other by the first shared coupling section, and wherein the third through electrodes are disposed asymmetrical to each other in plan view.

11. The solid-state imaging device according to claim 1 , wherein the first shared coupling section is embedded in the first semiconductor layer.

12. A solid-state imaging device, comprising:
a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, wherein the electric charge accumulation section accumulates a signal electric charge generated in the photoelectric converter;
a pixel separation section that is provided in the first semiconductor layer, wherein the pixel separation section partitions a plurality of the pixels from each other;
a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, wherein the pixel transistor reads the signal electric charge of the electric charge accumulation section;
a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, wherein the first shared coupling section straddles the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections;
a first substrate including the first semiconductor layer and a first wiring layer provided with the first shared coupling section;
a second substrate including the second semiconductor layer and a second wiring layer that is opposed to the first substrate with the second semiconductor layer interposed therebetween;
a third substrate that is opposed to the first substrate with the second substrate interposed therebetween, and includes a circuit that is electrically coupled to the second semiconductor layer
an impurity diffusion region that is provided in the first semiconductor layer for each of the pixels, and is disposed apart from the electric charge accumulation section;
a second shared coupling section that is provided in the first wiring layer, wherein the second shared coupling section straddles the pixel separation section and is electrically coupled to a plurality of the impurity diffusion regions; and
a second through electrode that electrically couples the second shared coupling section and a predetermined region of the second semiconductor layer to each other, wherein the second through electrode is provided in the first substrate and the second substrate.

13. The solid-state imaging device according to claim 12 , wherein an impurity region that is electrically coupled to the pixel transistor is further provided in the second semiconductor layer.

14. The solid-state imaging device according to claim 12 , wherein the first shared coupling section includes polysilicon and has an alloy region that is partially alloyed, and t

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Nakazawa Keiichi
• Zaitsu Koichiro
• Fujii Nobutoshi
• Hiura Yohei
• Mori Shigetaka
• Okamoto Shintaro
• Ohshima Keiji
• Manda Shuji
• Yamamoto Junpei
• Yuga Yui
• Miyake Shinichi
• Kambe Tomoki
• Ogata Ryo
• Miyaji Tatsuki
• Nakagawa Shinji
• Yamashita Hirofumi
• Hamamoto Yasushi
• Kimizuka Naohiko

Classifications

• H10F39/807 Primary

  Pixel isolation structures · CPC title

• H10F39/8037 Primary

  the integrated elements comprising a transistor · CPC title

• H10F39/811

  Interconnections · CPC title

• H10F39/802 Primary

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title