MEMS solenoid inductor and manufacturing method thereof

US12136509B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12136509-B2
Application numberUS-201917290553-A
CountryUS
Kind codeB2
Filing dateJul 8, 2019
Priority dateOct 30, 2018
Publication dateNov 5, 2024
Grant dateNov 5, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Embodiments of the present application provides a MEMS solenoid inductor, including: a silicon substrate, a soft magnetic core, and a solenoid; wherein the soft magnetic core is wrapped inside the silicon substrate, the silicon substrate is provided with a spiral channel, the soft magnetic core passes through a center of the spiral channel, and the solenoid is disposed in the spiral channel. By disposing the soft magnetic core and the solenoid of the inductor inside the silicon substrate completely, the thickness of the silicon substrate is fully utilized, and the obtained inductor has a larger winding cross-sectional area and improved magnetic flux, which increases the inductance value of the inductor; at the same time, the silicon substrate plays a protective role on the soft magnetic core and the solenoid, the strength of the inductor is improved, and the good impact resistance is provided.

First claim

Opening claim text (preview).

The invention claimed is: 1. A MEMS linear solenoid inductor, comprising: a silicon substrate, a soft magnetic core, and a solenoid; wherein the soft magnetic core is wrapped inside the silicon substrate, the silicon substrate is provided with a spiral channel, the soft magnetic core passes through a center of the spiral channel, and the solenoid is disposed in the spiral channel; wherein the silicon substrate comprises an upper silicon substrate and a lower silicon substrate, the soft magnetic core comprises an upper core and a lower core, and the upper core has the same shape as the lower core; wherein the upper silicon substrate is provided with a core slot on a lower surface thereof corresponding to a shape of the upper core, and the lower silicon substrate is provided with a core slot on an upper surface thereof corresponding to the shape of the lower core; and wherein the upper core and the lower core are disposed in the corresponding core slots, respectively, and the lower surface of the upper silicon substrate and the upper surface of the lower silicon substrate are bonded to each other, so that a lower surface of the upper core and an upper surface of the lower core are aligned with each other. 2. The MEMS linear solenoid inductor of claim 1 , wherein the spiral channel comprises a plurality of first horizontal trenches, a plurality of second horizontal trenches and a plurality of vertical through holes; wherein the first horizontal trenches are disposed on an upper surface of the silicon substrate, the second horizontal trenches are disposed on a lower surface of the silicon substrate, and the vertical through holes penetrate the upper and lower surfaces of the silicon substrate; and wherein a head and a tail of any one of the first horizontal trenches of the spiral channel communicate with two vertical through holes respectively, and the two vertical through holes communicate with two adjacent second horizontal trenches, respectively. 3. The MEMS linear solenoid inductor of claim 1 , further comprising two pins and two pin slots; wherein the two pin slots are disposed on an upper surface of the silicon substrate, the two pin slots communicate with a head and a tail of the spiral channel, respectively, and the two pins are disposed in the two pin slots, respectively. 4. The MEMS linear solenoid inductor of claim 1 , wherein the soft magnetic core is made of an iron-nickel alloy material or an iron-cobalt alloy material. 5. The MEMS linear solenoid inductor of claim 1 , wherein the solenoid is made of metallic copper. 6. A method for manufacturing the MEMS linear solenoid inductor of claim 1 , the method comprising the steps of: step 1, fabricating the silicon substrate having an upper silicon substrate and a lower silicon substrate, respectively; wherein the fabricating an upper silicon substrate includes: performing a first thermal oxidation on a first silicon wafer with a first preset thickness; according to a structure of the spiral channel of the silicon substrate, performing deep silicon etching on an upper surface, inside, and a lower surface of the first silicon wafer subjected to the first thermal oxidation to obtain a plurality of first horizontal trenches, upper halves of a plurality of vertical through holes, and a core slot; performing a second thermal oxidation on the first silicon wafer subjected to the deep silicon etching to obtain the upper silicon substrate; wherein the fabricating a lower silicon substrate includes: performing the first thermal oxidation on a second silicon wafer with the first preset thickness; according to the structure of the spiral channel of the silicon substrate, performing the deep silicon etching on an upper surface, inside, and a lower surface of the second silicon wafer subjected to the first thermal oxidation to obtain a core slot, lower halves of the plurality of vertical through holes, and a plurality of second horizontal trenches; performing the second thermal oxidation on the second silicon wafer subjected to the deep silicon etching to obtain the lower silicon substrate; step 2, electroplating inside the core slots of the upper silicon substrate and the lower silicon substrate to form the soft magnetic core having an upper core and a lower core, respectively; step 3, after aligning an upper surface of the upper silicon substrate and a lower surface of the lower silicon substrate with each other and aligning a lower surface of the upper core and an upper surface of the lower core with each other, bonding the upper silicon substrate and the lower silicon substrate at low temperature to form the spiral channel in the upper silicon substrate and the lower silicon substrate which are bonded; and step 4, electroplating in the spiral channel to form the solenoid, thereby obtaining the MEMS linear solenoid inductor; wherein the soft magnetic core is wrapped inside the silicon substrate, the soft magnetic core passes through the center of the spiral channel, and the solenoid is disposed in the spiral channel; wherein the plurality of first horizontal trenches are a plurality of parallel first horizontal trenches, and the plurality of second horizontal trenches are a plurality of parallel second horizontal trenches. 7. The method of claim 6 , wherein the electroplating inside the core slot of the upper silicon substrate to form an upper core comprises: after registering a metal mask with a core slot pattern with the core slot on a lower surface of the upper silicon substrate, tightly attaching the metal mask to the lower surface of the upper silicon substrate; and after magnetron sputtering metallic nickel or metallic cobalt with a second preset thickness as a seed layer on the lower surface of the upper silicon substrate, electroplating iron-nickel alloy or iron-cobalt alloy with a third preset thickness inside the core slot of the upper silicon substrate to obtain the upper core; correspondingly, the electroplating inside the core slot of the lower silicon substrate to form a lower core comprises: after registering a metal mask with a core slot pattern with the core slot on an upper surface of the lower silicon substrate, tightly attaching the metal mask to the upper surface of the lower silicon substrate; and after magnetron sputtering metallic nickel or metallic cobalt with the second preset thickness as a seed layer on the upper surface of the lower silicon substrate, electroplating iron-nickel alloy or iron-cobalt alloy with the third preset thickness inside the core slot of the lower silicon substrate to obtain the lower core. 8. The method of claim 6 , wherein the electroplating in the spiral channel to form the solenoid comprises: magnetron sputtering metallic titanium with a fourth preset thickness as an intermediate layer on the lower surface of the lower silicon substrate, magnetron sputtering metallic copper with a fifth preset thickness as a seed layer on the intermediate layer, and then electroplating metallic copper in the second horizontal trenches and the vertical through holes of the spiral channel until the metallic copper is filled to a position of a lower plane of the first horizontal trenches; and after magnetron sputtering metallic copper as a seed layer on the upper surface of the upper silicon substrate, electroplating metallic copper until the spiral channel is completely filled with the metallic copper to obtain the solenoid. 9. The method of claim 6 , wherein the fabricating an upper silicon substrate further comprises: according to the structure and position of two pins, performing deep silicon etching on the upper surface of the first silicon wafer subjected to a first oxidation to obtain two pin slots; and correspo

Assignees

Inventors

Classifications

  • Windings disposed upon ring cores · CPC title

  • structurally combined with ferromagnetic material · CPC title

  • Toroidal core with turns of coil around it · CPC title

  • with stacked layers · CPC title

  • H01F27/245Primary

    made from sheets, e.g. grain-oriented (H01F27/26 takes precedence) · CPC title

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What does patent US12136509B2 cover?
Embodiments of the present application provides a MEMS solenoid inductor, including: a silicon substrate, a soft magnetic core, and a solenoid; wherein the soft magnetic core is wrapped inside the silicon substrate, the silicon substrate is provided with a spiral channel, the soft magnetic core passes through a center of the spiral channel, and the solenoid is disposed in the spiral channel. By…
Who is the assignee on this patent?
Univ Beihang
What technology area does this patent fall under?
Primary CPC classification H01F27/245. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 05 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).