Fast bleed of power rails

Patent metadata

Field	Value
Publication number	US-12135596-B2
Application number	US-202217973943-A
Country	US
Kind code	B2
Filing date	Oct 26, 2022
Priority date	Oct 26, 2022
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

A voltage regulator system of an information handling system includes a Smart Power Stage (SPS) and a voltage regulator controller. The SPS includes a high-side transistor and a low-side transistor. The voltage regulator controller detects a normal power down of the information handling system and sets bleed state for the SPS to a first state. Based on the bleed state being set to the first state, the voltage regulator controller provides a first control voltage to the low-side transistor and a second control voltage to the high-side transistor. The first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region. In response to a predetermined amount of time expiring, the voltage regulator controller enters the SPS in an idle mode.

First claim

What is claimed is:

1. A voltage regulator system of an information handling system, the voltage regulator system comprising:
a Smart Power Stage (SPS) including a high-side transistor and a low-side transistor; and
a voltage regulator controller to communicate with the high-side and low-side transistors of the SPS, the voltage regulator controller to:
detect a normal power down of the information handling system;
set a bleed state for the SPS to a first state;
based on the bleed state being set to the first state, provide a first control voltage to the low-side transistor and a second control voltage to the high-side transistor,
wherein the first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region; and

in response to a predetermined amount of time expiring, enter the SPS in an idle mode.

2. The voltage regulator system of claim 1 , wherein prior to the bleed state being set to the first state, the voltage regulator controller further to determine whether a power fault has occurred, and in response to the power fault having occurred, execute a power fault handler, otherwise, set the bleed state to the first state.

3. The voltage regulator system of claim 1 , wherein prior to the bleed state being set to the first state, the voltage regulator controller further to determine whether an output rail has been bled to a ground voltage reference during a previous state of the bleed state.

4. The voltage regulator system of claim 1 , wherein the second control voltage is a pulse width modulated signal and a duty cycle of the pulse width modulated signal is based on a temperature of the high-side transistor.

5. The voltage regulator system of claim 4 , wherein the temperature of the high-side transistor increases while the pulse width modulate signal is in a high state.

6. The voltage regulator system of claim 5 , wherein the pulse width modulated signal is in a low state until the temperature of the high-side transistor is substantially equal to a reference temperature.

7. The voltage regulator system of claim 6 , wherein the second control voltage is a sequence of pulses, and a first length of time for each pulse in the sequence of pulses is shorter than a second length of time for each period of a low state in between sequential pulses.

8. The voltage regulator system of claim 1 , wherein when the low-side transistor is fully turned on and the high-side transistor is in the linear region, a voltage is bled from an input rail of the SPS.

9. A method comprising:
detecting, by a voltage regulator controller in an information handling system, a normal power down of the information handling system;
setting, by the voltage regulator controller, a bleed state for a Smart Power Stage (SPS) to a first state;
based on the bleed state being set to the first state, providing a first control voltage to the low-side transistor and a second control voltage to the high-side transistor, wherein the first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region; and
in response to a predetermined amount of time expiring, entering the SPS in an idle mode.

10. The method of claim 9 , wherein prior to the bleed state being set to the first state, the method further comprises: determining whether a power fault has occurred, and in response to the power fault having occurred, executing a power fault handler, otherwise, setting the bleed state to the first state.

11. The method of claim 9 , wherein the second control voltage is a pulse width modulated signal, wherein the method further comprises: controlling a duty cycle of the pulse width modulated signal based on a temperature of the high-side transistor.

12. The method of claim 11 , wherein the temperature of the high-side transistor increases while the pulse width modulate signal is in a high state.

13. The method of claim 12 , wherein the pulse width modulated signal is in a low state until the temperature of the high-side transistor is substantially equal to a reference temperature.

14. The method of claim 9 , wherein the second control voltage is a sequence of pulses.

15. The method of claim 14 , wherein a first length of time for each pulse in the sequence of pulses is shorter than a second length of time for each period of a low state in between sequential pulses.

16. The method of claim 9 , wherein when the low-side transistor is fully turned on and the high-side transistor is in the linear region, a voltage is bled from an input rail of the SPS.

17. A voltage regulator system of an information handling system, the voltage regulator system comprising:
a Smart Power Stage (SPS) including a high-side transistor and a low-side transistor; and
a voltage regulator controller to:
detect a normal power down of the information handling system;
if a power fault has occurred, then execute a power fault handler, otherwise set the bleed state for the SPS to a first state;
if the bleed state is set to the first state, then provide a first control voltage to the low-side transistor and a second control voltage to the high-side transistor,
wherein the first control voltage causes the low-side transistor to be fully turned on, and the second control voltage causes the high-side transistor to be in a linear region, wherein when the low-side transistor is fully turned on and the high-side transistor is in the linear region, a voltage is bled from an input rail of the SPS; and

in response to a predetermined amount of time expiring, enter the SPS in an idle mode.

18. The voltage regulator system of claim 17 , wherein the second control voltage is a pulse width modulated signal and a duty cycle of the pulse width modulated signal is based on a temperature of the high-side transistor.

19. The voltage regulator system of claim 17 , wherein the second control voltage is a sequence of pulses.

20. The voltage regulator system of claim 19 , wherein a first length of time for each pulse in the sequence of pulses is shorter than a second length of time for each period of a low state in between sequential pulses.

Assignees

• Dell Products Lp

Inventors

• Petivan Iii James L
• Guo Yun
• Wang Isaac Q
• Li Hang
• Rudiak Ronald Paul
• Whittenberg Justin

Classifications

• H02M3/156

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/0045

  Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode · CPC title

• H02M1/0032

  Control circuits allowing low power mode operation, e.g. in standby mode · CPC title

• H02M3/155

  using semiconductor devices only · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title