Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12133393-B2
Application number	US-202117502380-A
Country	US
Kind code	B2
Filing date	Oct 15, 2021
Priority date	Mar 24, 2021
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate including a first region and a second region such that the second region is separated from the first region;
forming a metal oxide film on the first region of the substrate and the second region of the substrate;
forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate and the metal oxide film of the second region is exposed; and
simultaneously annealing the upper metal material film and the exposed metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

2. The method of manufacturing a semiconductor device as claimed in claim 1 , wherein at least a part of the metal oxide film is in contact with an active pattern on the first region of the substrate and in contact with an active pattern on the second region of the substrate.

3. The method of manufacturing the semiconductor device as claimed in claim 2 , wherein:
the active pattern includes a fin pattern, and
the metal oxide film is on an upper surface of the fin pattern.

4. The method of manufacturing the semiconductor device as claimed in claim 2 , wherein:
the active pattern includes a lower pattern and a sheet pattern separated from the lower pattern in a first direction, and
forming the metal oxide film includes wrapping the metal oxide film around the sheet pattern.

5. The method of manufacturing the semiconductor device as claimed in claim 1 , further comprising forming a lower metal film on the first region of the substrate prior to forming the metal oxide film, wherein:
a portion of the metal oxide film overlaps the lower metal film below the metal oxide film on the first region of the substrate in a vertical direction, and
the metal oxide film is between the lower metal film and the upper metal material film on the first region.

6. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein a thickness of the ferroelectric insulating film in a vertical direction is the same as a thickness of the paraelectric insulating film in the vertical direction.

7. The method of manufacturing the semiconductor device as claimed in claim 6 , wherein the thicknesses of the ferroelectric insulating film and the paraelectric insulating film in the vertical direction are each within a range of 1.5 nm to 20 nm.

8. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein the annealing is performed within a temperature range of 300° C. to 1,100° C.

9. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein the metal oxide film includes hafnium oxide or zirconium oxide.

10. The method of manufacturing the semiconductor device as claimed in claim 1 , wherein forming the upper metal material film such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate includes patterning the upper metal material film to remove a portion of the upper metal material film that overlaps the metal oxide film on the second region of the substrate.

11. A method of manufacturing a semiconductor device, the method comprising:
forming a first dummy gate on a substrate such that the first dummy gate includes first spacers extending in a first direction and a first dummy electrode between the first spacers;
forming a second dummy gate on the substrate such that the second dummy gate includes second spacers extending in the first direction and different from the first spacers and a second dummy electrode between the second spacers;
removing the first dummy electrode and the second dummy electrode to form a first trench between the first spacers and a second trench between the second spacers;
forming a metal oxide film along an upper surface of the substrate and at least a part of side walls of the first spacers and the second spacers;
forming an upper metal material on the metal oxide film such that the upper metal material does not overlap the second spacers and the second trench in a vertical direction; and
simultaneously annealing the upper metal material and the metal oxide film to form a ferroelectric insulating film along at least a part of the side wall of the first spacers, and to form a paraelectric insulating film along at least a part of the side wall of the second spacers.

12. The method of manufacturing the semiconductor device as claimed in claim 11 , wherein:
the metal oxide film extends along the first trench defined by the first spacers, and
the metal oxide film in the first trench is in contact with the upper metal material.

13. The method of manufacturing the semiconductor device as claimed in claim 12 , wherein the metal oxide film is annealed while in contact with the upper metal material.

14. The method of manufacturing the semiconductor device as claimed in claim 11 , wherein a thickness of the ferroelectric insulating film in the vertical direction is the same as a thickness of the paraelectric insulating film in the vertical direction.

15. The method of manufacturing the semiconductor device as claimed in claim 11 , wherein:
the annealing is performed within a temperature range of 300° C. to 1,100° C., and the annealing includes rapid thermal annealing, laser annealing, or flash annealing.

16. The method of manufacturing the semiconductor device as claimed in claim 11 , wherein:
the metal oxide film includes hafnium oxide or zirconium oxide, and
the metal oxide film is doped with aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), or tin (Sn).

17. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming a gate electrode on the substrate;
forming an interlayer insulating film that covers the gate electrode on the substrate;
forming a first lower metal film and a second lower metal film on the interlayer insulating film such that the second lower metal film is separated from the first lower metal film;
forming a metal oxide film on the first lower metal film, the second lower metal film, and the interlayer insulating film;
forming an upper metal material film on the metal oxide film such that the upper metal material film does not overlap a portion of the metal oxide film on the second lower metal film; and
simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film overlapping the first lower metal film in a vertical direction, and to form a paraelectric insulating film overlapping the second lower metal film in the vertical direction.

18. The method of manufacturing the semiconductor device as claimed in claim 17 , wherein:
at least a part of the metal oxide film is annealed while in contact with the first lower metal film and the upper metal material film, and
the annealing includes rapid thermal annealing, laser annealing, or flash annealing.

19. The method of manufacturing the semiconductor device as claimed in claim 17 , wherein forming an upper metal material film such that the upper metal material film does not overlap the portion of the metal oxide film on the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Do Young
• NAM Kab Jin
• Pok In Bong
• Ha Dae Won
• Hasan Musarrat

Classifications

• H10P14/3452

  Microstructure · CPC title

• H10D64/0134

  with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor · CPC title

• H10D64/017 Primary

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/68

  characterised by the insulator, e.g. by the gate insulator · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title