Handling of out-of-order transport-layer packets using reorder buffer

Patent metadata

Field	Value
Publication number	US-12132665-B2
Application number	US-202217990768-A
Country	US
Kind code	B2
Filing date	Nov 21, 2022
Priority date	Nov 21, 2022
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

An apparatus includes a memory and control circuitry. The control circuitry is configured to receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, to detect that one or more of the packets deviate from the sequential order, to buffer the one or more deviating packets in the memory, and, using the memory, to reorder the packets and provide the packets in the sequential order to the network device.

First claim

The invention claimed is:

1. An apparatus, comprising:
a memory; and
control circuitry, to:
receive packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order;
detect that one or more of the packets deviate from the sequential order;
buffer the one or more deviating packets in the memory;
using the memory, reorder the packets and provide the packets in the sequential order to the network device; and
in response to detecting that a time that elapsed since initiating buffering of the one or more deviating packets exceeds a defined timeout, cause the network device to request retransmission of one or more packets that precede the one or more deviating packets.

2. The apparatus according to claim 1 , wherein the transport protocol is Remote Direct Memory Access (RDMA).

3. The apparatus according to claim 1 , wherein, in accordance with the transport protocol, the sequential order is defined by packet serial numbers (PSNs) specified in the packets.

4. The apparatus according to claim 1 , wherein the control circuitry is to reorder and provide the packets, by (i) retaining the one or more deviating packets in the memory until arrival of the one or more packets that precede the one or more deviating packets in the sequential order, and only then (ii) providing the one or more packets that precede the one or more deviating packets, followed by the one or more deviating packets.

5. The apparatus according to claim 1 , wherein the received packets comprise respective packet serial numbers (PSNs) that specify the sequential order, and wherein the control circuitry is to maintain an Expected PSN (EPSN), and to detect that a received packet deviates from the sequential order by detecting that the PSN of the packet differs from the EPSN.

6. The apparatus according to claim 1 , wherein the received packets comprise respective packet serial numbers (PSNs) that specify the sequential order, wherein at least some of the received packets are read responses that are received in response to a read request from the network device, and wherein the control circuitry is to obtain from the network device a-priori information indicative of the PSNs of the read responses, and to decide that one or more of the packets deviate from the sequential order based on the a-priori information.

7. The apparatus according to claim 6 , wherein the control circuitry is to obtain the a-priori information by monitoring the read request sent by the network device.

8. The apparatus according to claim 1 , wherein, in providing the packets to the network device, the control circuitry is to permit packets of one or more predefined types to deviate from the sequential order.

9. The apparatus according to claim 1 , wherein the control circuitry is to detect that a received packet deviates from the sequential order, by identifying that the packet is a data packet belonging to a Dynamically Connected (DC) flow for which a connection- request packet was not yet received.

10. The apparatus according to claim 1 , wherein the received packets are associated with multiple flows, and wherein the control circuitry is to detect and buffer the deviating packets, and to reorder and provide the packets, separately for each of the flows.

11. The apparatus according to claim 10 , wherein the control circuitry is to maintain, per flow, a respective context that stores one or more of:
an expected packet serial number (EPSN) for the flow;

a pointer to a memory location that stores the one or more deviating packets belonging to the flow;
a current smallest received packet serial number (PSN) among the packets of the flow;
a list of PSNs of one or more expected read responses; and
a highest PSN among the PSNs of received acknowledgement packets.

12. A method, comprising:
receiving packets, which are en-route to undergo transport-layer processing in a network device in accordance with a transport protocol that requires arrival of the packets in a sequential order, wherein the received packets comprising respective packet serial numbers (PSNs) (that specify the sequential order, and wherein at least some of the received packets are read responses that are received in response to a read request from the network device;
detecting that one or more of the packets deviate from the sequential order by (i) obtaining from the network device a-priori information indicative of the PSNs of the read responses, and (ii) deciding that one or more of the packets deviate from the sequential order based on the a-priori information;
buffering the one or more deviating packets in a memory; and
using the memory, reordering the packets and providing the packets in the sequential order to the network device.

13. The method according to claim 12 , wherein the transport protocol is Remote Direct Memory Access (RDMA).

14. The method according to claim 12 , wherein reordering and providing the packets comprise (i) retaining the one or more deviating packets in the memory until arrival of one or more packets that precede the one or more deviating packets in the sequential order, and only then (ii) providing the one or more packets that precede the one or more deviating packets, followed by the one or more deviating packets.

15. The method according to claim 12 , wherein detecting that one or more packets deviate from the sequential order comprises (i) maintaining an Expected PSN (EPSN) , and (ii) detecting that a received packet deviates from the sequential order by detecting that the PSN of the packet differs from the EPSN.

16. The method according to claim 12 , further comprising detecting that a time that elapsed since initiating buffering of the one or more deviating packets exceeds a defined timeout, and in response causing the network device to request retransmission of the one or more packets that precede the one or more deviating packets.

17. The method according to claim 12 , wherein obtaining the a-priori information comprises monitoring the read request sent by the network device.

18. The method according to claim 12 , wherein providing the packets to the network device comprises permitting packets of one or more predefined types to deviate from the sequential order.

19. The method according to claim 12 , wherein detecting that a received packet deviates from n the sequential order comprises identifying that the packet is a data packet belonging to a Dynamically Connected (DC) flow for which a connection-request packet was not yet received.

20. The method according to claim 12 , wherein the received packets are associated with multiple flows, and wherein detecting the deviating packets, buffer the deviating packets, and reordering and providing the packets, are performed separately for each of the flows.

21. The method according to claim 20 , further comprising maintaining, per flow, a respective context that stores one or more of:
an expected packet serial number (EPSN) for the flow;
a pointer to a memory location that stores the one or more deviating packets belonging to the flow;
a current smallest received packet serial number (PSN) among the packets of the flow;
a list of PSNs of one or more expected read responses; and
a highest PSN among the PSNs of received acknowledgement packets.

22. An apparatus, comprising:
a memory; and
control circuitry, configured to:
receive packets, which are en-route to under

Assignees

• Mellanox Technologies Ltd

Inventors

• Friedman Yamin
• Burstein Idan
• Shahar Ariel
• Moyal Roee
• Kremer Gil

Classifications

• H04L47/6275

  based on priority · CPC title

• H04L49/9036 Primary

  Common buffer combined with individual queues · CPC title

• H04L47/34

  ensuring sequence integrity, e.g. using sequence numbers · CPC title

• H04L47/624 Primary

  Altering the ordering of packets in an individual queue · CPC title

• H04L49/9057 Primary

  Arrangements for supporting packet reassembly or resequencing · CPC title