Memory module, memory system, and operation method of memory controller

Patent metadata

Field	Value
Publication number	US-12132501-B2
Application number	US-202217895227-A
Country	US
Kind code	B2
Filing date	Aug 25, 2022
Priority date	Oct 12, 2021
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

First claim

What is claimed is:

1. A memory system, comprising:
a memory module including a first memory device, a second memory device, a third memory device, and a fourth memory device, and a first error correction code (ECC) device; and
a memory controller configured to exchange first user data with each of the first memory device, the second memory device, the third memory device, and the fourth memory device through 8 data lines and to exchange first ECC data with the first ECC device of the memory module through 4 data lines,
wherein the memory controller includes an ECC engine configured to detect and correct a 32-random bit error of the first user data based on the first ECC data,
wherein the first ECC data include first detection data and first correction data,
wherein the ECC engine of the memory controller is configured to generate the first detection data and the first correction data by performing an ECC operation on the first user data in units of 32 bits and to generate second detection data based on the first user data read from the memory module, and
wherein, when the second detection data are different from the first detection data read from the memory module, the ECC engine of the memory controller is configured to perform correction of the 32-random bit error of the first user data based on the first correction data read from the memory module.

2. The memory system of claim 1 ,
wherein the first detection data are generated by performing a CRC-32 calculation on the first user data, and
wherein the first correction data are generated by performing an even parity calculation on the first user data.

3. The memory system of claim 1 , wherein each of the first memory device, the second memory device, the third memory device, and the fourth memory device includes:
a first sub-array, a second sub-array, a third sub-array, a fourth sub-array, a fifth sub-array, a sixth sub-array, a seventh sub-array, and an eighth sub-array corresponding to a first data line, a second data line, a third data line, a fourth data line, a fifth data line, a sixth data line, a seventh data line, and an eighth data line, respectively; and
a plurality of sub-word line drivers configured to control a plurality of word lines connected with the first sub-array to eighth sub-array.

4. The memory system of claim 3 , wherein, in the plurality of sub-word line drivers,
first sub-word line drivers configured to control word lines connected with the first sub-array and second sub-array,
second sub-word line drivers configured to control word lines connected with the third sub-array and fourth sub-array,
third sub-word line drivers configured to control word lines connected with the fifth sub-array and sixth sub-array, and
fourth sub-word line drivers configured to control word lines connected with the seventh sub-array and eighth sub-array are physically separated from each other.

5. The memory system of claim 4 , wherein the 32-random bit error occurs due to a fault of one of the first memory device to fourth memory device.

6. The memory system of claim 5 , wherein, when the one of the first memory device to fourth memory device is faulty, the 32-random bit error occurs in bits output from the first data line and second data line, the third data line and fourth data line, the fifth data line and sixth data line, or the seventh data line and eighth data line of the first data line to eighth data line connected with the one of the first memory device to fourth memory device which is faulty.

7. The memory system of claim 1 , wherein a size of the first user data is 64 bytes, and a size of the first ECC data is 8 bytes.

8. The memory system of claim 1 , wherein the memory module has a form factor of an unbuffered dual in-line memory module (UDIMM) or a small outline dual in-line memory module (SODIMM).

9. The memory system of claim 1 , wherein the ECC engine of the memory controller comprises:
an encoding logic configured to generate the first detection data and the first correction data; and
a decoding logic configured to generate the second detection data.

10. The memory system of claim 9 , wherein the encoding logic comprises:
a 32-bit detection encoding logic configured to generate the first detection data; and
a 32-bit correction encoding logic configured to generate the first correction data.

11. The memory system of claim 9 , wherein the decoding logic comprises:
a 32-bit detection decoding logic configured to generate the second detection data and determine whether the 32-random bit error is present in the first user data; and
a 32-bit correction decoding logic configured to perform the correction of the 32-random bit error of the first user data when the 32-random bit error is detected.

12. An operation method of a memory controller configured to control a memory module having a form factor of an unbuffered dual in-line memory module (UDIMM), the method comprising:
generating detection data and correction data based on user data;
writing the user data, the detection data, and the correction data into the memory module;
reading the user data, the detection data, and the correction data from the memory module;
detecting, by the memory controller, a random bit error of the user data based upon a difference between the detection data read from the memory module and the detection data written into the memory module;
correcting, by the memory controller, the random bit error of the user data based on the correction data to produce corrected user data; and
outputting the corrected user data.

13. The method of claim 12 ,
wherein the memory module includes a plurality of memory devices and an error correction code (ECC) device, and
wherein the plurality of memory devices are connected with the memory controller through “a×N” data lines, wherein “a” is a number of the plurality of memory devices and N is a natural number greater than 1, and the ECC device is connected with the memory controller through “M” data lines, wherein M being is a natural number smaller than the N.

14. The method of claim 13 , wherein the writing of the user data, the detection data, and the correction data in the memory module includes:
transmitting a write command to the memory module; and
transmitting the user data through the “a×N” data lines connected with each of the plurality of memory devices and transmitting the detection data and the correction data through the “M” data lines connected with the ECC device.

15. The method of claim 14 , wherein the “a” is 4, the “N” is 8, and the “M” is 4.

16. The method of claim 14 , wherein the reading of the user data, the detection data, and the correction data from the memory module includes:
transmitting a read command to the memory module; and
receiving the user data through the “a×N” data lines connected with each of the plurality of memory devices and receiving the detection data and the correction data through the “M” data lines connected with the ECC device.

17. The method of claim 12 , wherein the correction data are generated by performing an even parity calculation on the user data, and
wherein the random bit error is corrected by performing the even parity calculation on the user data based on the correction data.

18. A memory module having a form factor of an unbuffered dual in-line memory module (UDIMM), comprising:
a first memory device connected with an external memory controller through a first data line, a second data line, a third data line, a fourth data line, a fifth data line, a sixth data line, a sevent

Assignees

• Samsung Electronics Co Ltd

Inventors

• Shin Wonjae
• Kim Sung-Joon
• Kim Heedong
• Bae Minsu
• Seo Ilwoong
• Lee Mijin
• Lee Seung Ju
• Lee Hyan Suk
• CHOI Insu
• Han Kideok

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C8/08

  Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines · CPC title

• G06F11/10 Primary

  Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title