Weak erase pulse

Patent metadata

Field	Value
Publication number	US-12131785-B2
Application number	US-202217829837-A
Country	US
Kind code	B2
Filing date	Jun 1, 2022
Priority date	Jun 1, 2022
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

Systems, apparatuses and methods may provide for technology that biases a word line of a block in NAND memory to a first voltage level, biases a source-side select gate and a drain-side select gate of the block to a second voltage level, and issues a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse. In one example, the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

First claim

We claim:

1. A memory chip controller comprising:
one or more substrates, and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
bias a word line of a block in NAND memory to a first voltage level,
bias a source-side select gate and a drain-side select gate of the block to a second voltage level, and
issue a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse.

2. The memory chip controller of claim 1 , wherein the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

3. The memory chip controller of claim 1 , wherein the first voltage level is less than a fifth voltage level of an unselected word line bias associated with the standard erase pulse.

4. The memory chip controller of claim 1 , wherein the logic is to set a duration of the discharge erase pulse based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

5. The memory chip controller of claim 1 , wherein the logic is to set a frequency of the discharge erase pulse based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

6. The memory chip controller of claim 1 , wherein the logic is to set the first voltage level, the second voltage level, and the third voltage level based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

7. The memory chip controller of claim 1 , wherein the logic is to issue the discharge erase pulse to bitlines and sources of a plurality of blocks in the NAND memory.

8. A computing system comprising:
a NAND memory, and
a memory chip controller coupled to the NAND memory, wherein the memory chip controller includes logic coupled to one or more substrates, the logic to:
bias a word line of a block in the NAND memory to a first voltage level,
bias a source-side select gate and a drain-side select gate of the block to a second voltage level, and
issue a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse.

9. The computing system of claim 8 , wherein the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

10. The computing system of claim 8 , wherein the first voltage level is less than a fifth voltage level of an unselected word line bias associated with the standard erase pulse.

11. The computing system of claim 8 , wherein the logic is to set a duration of the discharge erase pulse based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

12. The computing system of claim 8 , wherein the logic is to set a frequency of the discharge erase pulse based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

13. The computing system of claim 8 , wherein the logic is to set the first voltage level, the second voltage level, and the third voltage level based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

14. The computing system of claim 8 , wherein the logic is to issue the discharge erase pulse to bitlines and sources of a plurality of blocks in the NAND memory.

15. A method comprising:
biasing a word line of a block in NAND memory to a first voltage level,
biasing a source-side select gate and a drain-side select gate of the block to a second voltage level, and
issuing a discharge erase pulse to bitlines and a source of the block, wherein the discharge erase pulse is issued at a third voltage level, wherein the third voltage level is greater than the first voltage level and the second voltage level, and wherein the third voltage level is less than a fourth voltage level of a standard erase pulse.

16. The method of claim 15 , wherein the discharge erase pulse injects holes into pillars of the block and bypasses an erase of cells in the pillars of the block.

17. The method of claim 15 , wherein the first voltage level is less than a fifth voltage level of an unselected word line bias associated with the standard erase pulse.

18. The method of claim 15 , further including setting a duration of the discharge erase pulse based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

19. The method of claim 15 , further including setting a frequency of the discharge erase pulse based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

20. The method of claim 15 , set the first voltage level, the second voltage level, and the third voltage level based on one or more of a temperature, a workload, a deck status or a wear state associated with the block.

Assignees

• Intel NDTM US LLC

Inventors

• Zhang Chao
• Parat Krishna
• Fastow Richard
• Basco Ricardo
• Sun Xin
• Kim Heonwook
• Liu Zhan

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/349

  Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title