Method and device for clock calibration, and storage medium

Patent metadata

Field	Value
Publication number	US-12131683-B2
Application number	US-202117497920-A
Country	US
Kind code	B2
Filing date	Oct 9, 2021
Priority date	Oct 9, 2020
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A method for clock calibration is provided. In the technical solution according to the present disclosure, a target driving chip includes a plurality of clock calibration circuits, wherein each of the clock calibration circuits is configured with one clock frequency. Prior to sending a clock calibration signal, a controller sends a reference clock frequency to a driving chip over a configuration instruction, such that the driving chip determines a target clock calibration circuit for clock calibration based on the configuration instruction.

First claim

What is claimed is:

1. A method for clock calibration, applicable to a controller, the method comprising:
sending display data to a target driving chip based on an initial clock frequency, the target driving chip comprising a plurality of clock calibration circuits, each of the clock calibration circuits being configured with one clock frequency;
sending a configuration instruction to the target driving chip, the configuration instruction comprising a reference clock frequency; and
sending a clock calibration signal of a first target clock frequency to the target driving chip, the first target clock frequency being different from the initial clock frequency, wherein
the configuration instruction is configured to instruct the target driving chip to adjust a local clock frequency of the target driving chip to the first target clock frequency by a target clock calibration circuit, and a difference between a clock frequency configured for the target clock calibration circuit and the reference clock frequency is less than a difference between a clock frequency configured for other clock calibration circuits in the target driving chip and the reference clock frequency.

2. The method according to claim 1 , wherein sending the clock calibration signal of the first target clock frequency to the target driving chip comprises:
sending the clock calibration signal of the first target clock frequency to the target driving chip within one first synchronization cycle; and
repeating the step of sending the clock calibration signal of the first target clock frequency within one first synchronization cycle in the case that a first feedback signal configured to indicate completion of calibration of the first target clock frequency is not received, until the first feedback signal is received from the target driving chip.

3. The method according to claim 2 , wherein in the case that a number of repetition times within the first synchronization cycle is greater than a number threshold, the method further comprises:
continuously sending the clock calibration signal of the first target clock frequency to the target driving chip until the first feedback signal is received.

4. The method according to claim 2 , wherein in the case that the number of repetition times within the first synchronization cycle is greater than the number threshold, the method further comprises:
sending the clock calibration signal of the first target clock frequency to the target driving chip within one second synchronization cycle, and repeating the step of sending the clock calibration signal of the first target clock frequency within the second synchronization cycle in the case that the first feedback signal from the target driving chip is not received, until the first feedback signal is received, wherein a length of the second synchronization cycle is greater than a length of the first synchronization cycle.

5. The method according to claim 1 , wherein the reference clock frequency is equal to the first target clock frequency.

6. The method according to claim 1 , wherein
prior to sending the clock calibration signal of the first target clock frequency to the target driving chip, the method further comprises:
sending a clock calibration signal of a second target clock frequency to the target driving chip; and

sending the clock calibration signal of the first target clock frequency to the target driving chip comprises:
sending the clock calibration signal of the first target clock frequency to the target driving chip in the case that a second feedback signal configured to indicate completion of calibration of the second target clock frequency is received from the target driving chip, wherein
the initial clock frequency, the second target clock frequency, and the first target clock frequency are sequentially increased or decreased.

7. The method according to claim 6 , wherein a difference between the first target clock frequency and the second target clock frequency is equal to a difference between the second target clock frequency and the initial clock frequency.

8. The method according to claim 6 , wherein the reference clock frequency is equal to the second target clock frequency.

9. The method according to claim 1 , wherein in response to sending the clock calibration signal of the first target clock frequency to the target driving chip, the method further comprises:
sending a link stable pattern to the target driving chip in the case that the first feedback signal configured to indicate completion of calibration of the first target clock frequency is received from the target driving chip.

10. The method according to claim 1 , wherein
the controller is connected to a plurality of driving chips which are connected to a display panel, each of the driving chips being configured to drive a display region in the display panel; and
the method further comprises:
determining that a resolution and/or a refresh rate of a target display region in the display panel need/needs to be adjusted; and
determining a driving chip configured to drive the target display region as the target driving chip.

11. The method according to claim 1 , wherein
the display data comprises a plurality of rows of pixel data corresponding to a plurality of rows of pixels one by one;
sending the display data to the target driving chip based on the initial clock frequency comprises:
sending the pixel data to the target driving chip row by row based on the initial clock frequency in a displaying phase;

sending the configuration instruction to the target driving chip comprises:
sending the configuration instruction to the target driving chip in response to sending pixel data in the last row in the displaying phase; and

sending the clock calibration signal of the first target clock frequency to the target driving chip comprises:
sending the clock calibration signal of the first target clock frequency to the target driving chip in a blanking phase upon the displaying phase.

12. The method according to claim 4 , wherein
the controller is connected to a plurality of driving chips which are connected to a display panel, each of the driving chips being configured to drive a display region in the display panel; and
the method further comprises:
determining that a resolution and/or a refresh rate of a target display region in the display panel need/needs to be adjusted; and
determining a driving chip configured to drive the target display region as the target driving chip;

prior to sending the clock calibration signal of the first target clock frequency to the target driving chip, the method further comprises:
sending a clock calibration signal of a second target clock frequency to the target driving chip, wherein a difference between the first target clock frequency and the second target clock frequency is equal to a difference between the second target clock frequency and the initial clock frequency, and the reference clock frequency is equal to the second target clock frequency;

sending the clock calibration signal of the first target clock frequency to the target driving chip comprises:
sending the clock calibration signal of the first target clock frequency to the target driving chip in the case that a second feedback signal configured to indicate completion of calibration of the second target clock frequency is received from the target driving chip; and

in response to sending the clock calibration signal of the first target clock frequency to the target driving chip, the method further comprises:
sending a link stable pattern to the target driving chip in the case that the first feedback signal configured to indi

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Duan Xin
• Sun Jigang
• Zong Shaolei
• Sun Wei

Classifications

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G06F1/14

  Time supervision arrangements, e.g. real time clock · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F1/08 Primary

  Clock generators with changeable or programmable clock frequency · CPC title