Delay time detection circuit, stamping information generation device, and delay time detection method

Patent metadata

Field	Value
Publication number	US-12130653-B2
Application number	US-201917289509-A
Country	US
Kind code	B2
Filing date	Aug 26, 2019
Priority date	Nov 12, 2018
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A delay time detection circuit includes below configurations. A clock generation unit generates a sub scale clock signal, based on a system clock signal. A count unit generates a count signal while sequentially and repeatedly incrementing a count number, based on the sub scale clock signal. A sub scale signal generation unit receives the count signal, and generates sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with a second period and that are shifted in timing relative to one another according to the second period. A delay time calculation unit receives the input clock signal, and calculates a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals.

First claim

What is claimed is:

1. A delay time detection circuit that detects a delay time of an input clock signal having a first period with respect to a system clock signal by use of the system clock signal corresponding to a main scale and having the first period, and a sub scale clock signal corresponding to a sub scale and having a second period differing from the first period, the delay time detection circuit comprising:
a clock generation unit configured to generate a sub scale clock signal, based on the system clock signal;
a count unit configured to generate a count signal while sequentially and repeatedly incrementing a preset count number, based on the sub scale clock signal;
a sub scale signal generation unit configured to receive the count signal, and to generate sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with the second period and that are shifted in timing relative to one another according to the second period;
a delay time calculation unit configured to receive the input clock signal, and to calculate a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals having a timing coinciding with the input clock signal among a plurality of the sub scale signals;
a count number calculation unit configured to receive a value of the second period as a setting value, and to determine the count number, based on the received setting value and the first period,
wherein the delay time calculation unit processes, as a timing coinciding with the input clock signal, either
a case where two or more rising edges of the input clock signal are included within a duration being associated with the second period of the rectangular wave, or
a case where two or more falling edges of the input clock signal are included within a duration being associated with the second period of the rectangular wave,
wherein the sub scale clock signal generated by the clock generation unit has the second period being longer than the first period and shorter than a period twice the first period,
wherein the count number calculation unit sets, as the count number, a minimum value of a first value when a remainder of a division becomes zero,
wherein the division is defined by dividing a second value by a third value,
wherein the first value is a quotient of the division,
wherein the third value is a difference between the setting value and the first period, and
wherein the second value is a multiplicative period of a value of the first period by any natural number becomes zero.

2. The delay time detection circuit according to claim 1 , wherein the sub scale signal generation unit generates, as a duration being associated with the second period, the sub scale signal having the rectangular wave for a duration coinciding with the second period.

3. The delay time detection circuit according to claim 1 , wherein the sub scale signal generation unit includes
a clock reception unit configured to receive the sub scale clock signal from the clock generation unit,
a count signal reception unit configured to receive the count signal from the count unit, and
a sub scale signal output unit, equal in number to the count number, to supply the sub scale signal to the delay time calculation unit.

4. A stamping information generation device comprising:
the delay time detection circuit according to claim 1 ;
a timer that generates timer information, based on the system clock signal; and
an adder that:
calculates an additional value by adding the delay time and the timer information;
divides the additional value into an integral part and a decimal part; and
outputs each of the integral part and the decimal part.

5. The stamping information generation device according to claim 4 , further comprising:
a time information generation unit configured to receive the integral part, and to generate time information, based on the received integral part; and
a decimal retention unit configured to receive the decimal part, and to retain a value of the decimal part,
wherein stamping information in which the time information and the value of the decimal part are added is output based on an input signal synchronized with the input clock signal.

6. A delay time detection method comprising:
a clock generation step of generating, based on a system clock signal corresponding to a main scale and having a first period, a sub scale clock signal having a second period differing from the first period;
a count step of generating a count signal while sequentially and repeatedly incrementing a preset count number, based on the sub scale clock signal;
a sub scale signal generation step of receiving the count signal, and generating sub scale signals, equal in number to the count number, that each have, at a rate of once in the count number, a rectangular wave for a duration being associated with the second period and that are shifted in timing relative to one another according to the second period;
a delay time calculation step of receiving an input clock signal having the first period, and calculating a delay time within a range of the first period of the input clock signal with respect to the system clock signal, based on one of the sub scale signals having a timing coinciding with the input clock signal among a plurality of the sub scale signals;
a count number calculation step of receiving a value of the second period as a setting value, and to determine the count number, based on the received setting value and the first period,
wherein the delay time calculation step processes, as a timing coinciding with the input clock signal, either
a case where two or more rising edges of the input clock signal are included within a duration being associated with the second period of the rectangular wave, or
a case where two or more falling edges of the input clock signal are included within a duration being associated with the second period of the rectangular wave,
wherein the sub scale clock signal generated by the clock generation step has the second period being longer than the first period and shorter than a period twice the first period,
wherein the count number calculation unit step, as the count number, a minimum value of a first value when a remainder of a division becomes zero,
wherein the division is defined by dividing a second value by a third value,
wherein the first value is a quotient of the division,
wherein the third value is a difference between the setting value and the first period, and
wherein the second value is a multiplicative period of a value of the first period by any natural number.

Assignees

• Nec Platforms Ltd

Inventors

• Takahashi Masayuki

Classifications

• H03K2005/00013

  Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse · CPC title

• H03K21/02

  Input circuits · CPC title

• H03K5/01

  Shaping pulses (discrimination against noise or interference H03K5/125) · CPC title

• G04F10/06

  by measuring phase {(G04F10/005 takes precedence)} · CPC title

• G04C13/023

  via existing transmission lines · CPC title