Data transmission and recovery with algorithmic transition codes

US12125459B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12125459-B2
Application numberUS-202217863791-A
CountryUS
Kind codeB2
Filing dateJul 13, 2022
Priority dateSep 24, 2021
Publication dateOct 22, 2024
Grant dateOct 22, 2024

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An embodiment of the present disclosure provides a data transmission method that transmits data in a clock-embedded manner, including: dividing the data into a plurality of data packets having a bit number of ‘a’; determining a transition code including information on a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bits ([a−1:1]) among the data packets; converting the plurality of data packets into transition ensuring data packets by using the transition code; and transmitting the transition code and the transition ensuring data packets.

First claim

Opening claim text (preview).

What is claimed is: 1. A data transmission method that transmits data in a clock-embedded manner, comprising: dividing the data into a plurality of data packets each having a bit number of ‘a’, where ‘a’ is greater than one; determining a transition code including information on a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bit or bits ([a−1:1]) among the data packets; converting the plurality of data packets into transition ensuring data packets by using the transition code; and transmitting the transition code and the transition ensuring data packets. 2. The data transmission method of claim 1 , wherein: when the bit number is ‘a’, the number of data values that is representable by the data is 2a. 3. The data transmission method of claim 1 , wherein: the determining of the transition code further includes grouping the data packets to include 2a−1-1 of the data packets per one transition code. 4. The data transmission method of claim 3 , wherein: the first transition facilitating data packet and the second transition facilitating data packet are not included in a group of the data packet. 5. The data transmission method of claim 1 , wherein: in the transition code, the least significant bit ([0]) is set as a complement of one of bits included in the high-order bit or bits ([a−1:1]). 6. The data transmission method of claim 1 , wherein: the bit number ‘a’ is greater than two, the converting of the plurality of data packets into the transition ensuring data packets includes: in a case in which a data packet not including a transition among the plurality of data packets exists, converting the data packet into the first transition facilitating data packet when all bits of the data packet not including the transition are 0, and converting the data packet into the second transition facilitating data packet when all bits of the data packet not including the transition are 1. 7. The data transmission method of claim 6 , wherein the data packet in which all the bits are 0 corresponds to data displaying a black grayscale, and the data packet in which all the bits are 1 corresponds to data displaying a white grayscale. 8. The data transmission method of claim 6 , wherein the least significant bit ([0]) of the first transition facilitating data packet is 0, and the least significant bit ([0]) of the second transition facilitating data packet is 1. 9. The data transmission method of claim 6 , wherein the converting of the plurality of data packets into the transition ensuring data packets includes converting a data packet including a transition among the plurality of data packets into a transition ensuring data packet having the same value. 10. A data recovery method that recovers data transmitted in a clock-embedded manner, comprising: as a method of recovering transition ensuring data to data packets, receiving a transition code and the transition ensuring data packets; and recovering the transition ensuring data packets to the data packets by using the transition code, wherein the number of bits of each of the plurality of data packets is ‘a’, where ‘a’ is greater than one, and wherein the transition code includes a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bit or bits ([a−1:1]) among the data packets. 11. The data recovery method of claim 10 , wherein: in the transition code, the least significant bit ([0]) is set as a complement of one of bits included in the high-order bit or bits ([a−1:1]). 12. The data recovery method of claim 10 , wherein: the number of bits ‘a’ is greater than two, the recovering of the transition ensuring data packets to the data packets includes: comparing the transition ensuring data with the transition code; converting the transition ensuring data into a data packet in which all bits thereof are 0, when the high-order bits ([a−1:1]) of the transition ensuring data is the same as the high-order bits ([a−1:1]) of the transition code and when the least significant bit ([0]) of the transition ensuring data is 0; and converting the transition ensuring data into a data packet in which all bits thereof are 1, when the high-order bits ([a−1:1]) of the transition ensuring data is the same as the high-order bits ([a−1:1]) of the transition code and when the least significant bit ([0]) of the transition ensuring data is 1. 13. The data recovery method of claim 12 , wherein the data packet in which all the bits are 0 corresponds to data displaying a black grayscale, and the data packet in which all the bits are 1 corresponds to data displaying a white grayscale. 14. The data recovery method of claim 12 , wherein the recovering of the transition ensuring data packets to the data packets includes converting the transition ensuring data packets into a data packet having the same value as the transition ensuring data when the high-order bits ([a−1:1]) of the transition ensuring data is not the same as the high-order bits ([a−1:1]) of the transition code. 15. The data recovery method of claim 10 , wherein when the number of the bits is ‘a’, the number of data values that is representable by the data is 2a. 16. The data recovery method of claim 15 , wherein in the receiving of the transition code and the transition ensuring data, the transition code and the transition ensuring data are received in units of groups, and the group includes 2a−1-1 of the transition ensuring data per one transition code. 17. A transceiver comprising: a transmitter including a transmission controller, at least one encoder connected to the transmission controller, and at least one transmitter unit connected to the at least one encoder, respectively; and a receiver coupled in signal communication with the transmitter, the receiver including at least one receiver unit, at least one decoder connected to the at least one receiver unit, respectively, and a reception controller connected to the at least one decoder, wherein the at least one encoder is configured to divide clock-embedded data into a plurality of data packets each having a bit number of ‘a’, where ‘a’ is greater than one, determine a transition code including information on a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bit or bits ([a−1:1]) among the data packets, and convert the plurality of data packets into transition ensuring data packets by using the transition code. 18. The transceiver of claim 17 , wherein the at least one transmitter unit is configured to transmit the transition code and the transition ensuring data packets. 19. The transceiver of claim 18 , wherein the at least one receiver unit is configured to receive a transition code and the transition ensuring data packets, wherein the at least one decoder unit is configured to recover the transition ensuring data packets to the data packets by using the transition code, wherein the number of bits of each of the plurality of data packets is ‘a’, wherein ‘a’ is greater than one, wherein the transition code includes a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bit or bits ([a−1:1]) among the data packets. 20. The transceiver of claim 19 , wherein the number of bits ‘a’ is greater than two.

Assignees

Inventors

Classifications

  • using an embedded synchronisation · CPC title

  • Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell · CPC title

  • by transition coding, i.e. the time-position or direction of a transition being encoded before transmission · CPC title

  • using binary codes · CPC title

  • Synchronisation information channels, e.g. clock distribution lines · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12125459B2 cover?
An embodiment of the present disclosure provides a data transmission method that transmits data in a clock-embedded manner, including: dividing the data into a plurality of data packets having a bit number of ‘a’; determining a transition code including information on a first transition facilitating data packet and a second transition facilitating data packet having the same high-order bits ([a…
Who is the assignee on this patent?
Samsung Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04L7/033. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 22 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).