Speculative execution of hit and intersection shaders on programmable ray tracing architectures

Patent metadata

Field	Value
Publication number	US-12125133-B2
Application number	US-202318371614-A
Country	US
Kind code	B2
Filing date	Sep 22, 2023
Priority date	Dec 28, 2018
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

Apparatus and method for speculative execution of hit and intersection shaders on programmable ray tracing architectures. For example, one embodiment of an apparatus comprises: single-instruction multiple-data (SIMD) or single-instruction multiple-thread (SIMT) execution units (EUs) to execute shaders; and ray tracing circuitry to execute a ray traversal thread, the ray tracing engine comprising: traversal/intersection circuitry, responsive to the traversal thread, to traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and to intersect the ray with a primitive contained within at least one of the nodes; and shader deferral circuitry to defer and aggregate multiple shader invocations resulting from the traversal thread until a particular triggering event is detected, wherein the multiple shaders are to be dispatched on the EUs in a single shader batch upon detection of the triggering event.

First claim

What is claimed is:

1. An apparatus comprising:
execution circuitry to execute shaders; and
ray tracing circuitry to execute a ray traversal thread, the ray tracing circuitry is to:
responsive to the ray traversal thread, traverse a ray through an acceleration data structure comprising a plurality of hierarchically arranged nodes and intersect the ray with a primitive contained within at least one of the plurality of hierarchically arranged nodes; and
accumulate multiple shader invocations resulting from the ray traversal thread traversing the ray until a particular triggering event is detected, wherein the accumulated multiple shader invocations resulting from the ray traversal thread traversing the ray cause a single batch to be dispatched to the execution circuitry.

2. The apparatus of claim 1 , wherein the particular triggering event comprises a particular temporal event or processing event.

3. The apparatus of claim 1 , further comprising:
a scheduler to dispatch the single batch on the execution circuitry responsive to the particular triggering event.

4. The apparatus of claim 1 , wherein the ray traversal thread is to be suspended pending execution results of the single batch executed on the execution circuitry, wherein a first traversal context of the ray traversal thread is to be maintained while the ray traversal thread is suspended.

5. The apparatus of claim 4 , wherein the ray tracing circuitry is to accumulate the multiple shader invocations based on the multiple shader invocations being associated with the first traversal context.

6. The apparatus of claim 1 , wherein a primary ray shader thread executed on the execution circuitry is to spawn the ray traversal thread.

7. The apparatus of claim 1 , further comprising:
sorting circuitry to regroup data associated with the single batch to increase occupancy for operations performed by the execution circuitry.

8. The apparatus of claim 1 , wherein accumulating the multiple shader invocations comprises storing a data entry in a data structure in a memory, the data structure comprising at least one entry for each shader, each entry usable to identify shader information required to execute a corresponding shader.

Assignees

• Intel Corp

Inventors

• Liktor Gabor
• Vaidyanathan Karthik
• Amstutz Jefferson
• Kuwahara Atsuo
• Doyle Michael
• Schluessler Travis

Classifications

• G06T2210/21

  Collision detection, intersection · CPC title

• G06T15/06 Primary

  Ray-tracing · CPC title

• G06T1/60

  Memory management · CPC title

• G06T15/005 Primary

  General purpose rendering architectures · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title