Gate driver system for detecting a short circuit condition

Patent metadata

Field	Value
Publication number	US-12119810-B2
Application number	US-202217933615-A
Country	US
Kind code	B2
Filing date	Sep 20, 2022
Priority date	Sep 20, 2022
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

A driver system includes a first half-bridge that generates a first load current at a first output node, a second half-bridge that generates a second load current at a second output node, a first voltage charging device coupled to the first output node, and a second voltage charging device coupled to the second output node. A method of detecting a short circuit condition in the driver system includes detecting a first charging time at which a first charging voltage of the first voltage charging device is charged to a first threshold voltage; detecting a second charging time at which a second charging voltage of the second voltage charging device is charged to a second threshold voltage; and detecting the short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold.

First claim

What is claimed is:

1. A driver system configured to drive a motor, the driver system comprising:
a first half-bridge circuit comprising a first high-side transistor and a first low-side transistor coupled at a first output node, wherein the first high-side transistor and the first low-side transistor are configured to cooperatively generate a first load current at the first output node for driving the motor;
a second half-bridge circuit comprising a second high-side transistor and a second low-side transistor coupled at a second output node, wherein the second high-side transistor and the second low-side transistor are configured to cooperatively generate a second load current at the second output node for driving the motor;
a first voltage charging device coupled to a first power supply and to the first output node;
a second voltage charging device coupled to a second power supply and to the second output node; and
a diagnostic circuit configured to monitor a first charging voltage of the first voltage charging device and a second charging voltage of the second voltage charging device, detect a first charging time at which the first charging voltage is charged to a first threshold voltage, detect a second charging time at which the second charging voltage is charged to a second threshold voltage, and detect a short circuit condition on a condition that a time difference between the first charging time and the second charging time is less than a time difference threshold.

2. The driver system of claim 1 , wherein the diagnostic circuit is configured to detect a normal operating condition on a condition that the time difference between the first charging time and the second charging time is equal to or greater than the time difference threshold.

3. The driver system of claim 1 , wherein the diagnostic circuit is configured to detect the short circuit condition on a condition that the second charging time occurs at a time delay relative to the first charging time that is less than the time difference threshold.

4. The driver system of claim 3 , wherein the diagnostic circuit is configured to detect a normal operating condition on a condition that the second charging time occurs at a time delay relative to the first charging time that is equal to or greater than the time difference threshold.

5. The driver system of claim 1 , further comprising:
a driver circuit configured to generate control signals to drive the first high-side transistor, the first low-side transistor, the second high-side transistor, and the second low-side transistor between respective switching states, including at least an on state and an off state,
wherein while the diagnostic circuit monitors the first charging voltage of the first voltage charging device and the second charging voltage of the second voltage charging device, the driver circuit is configured to maintain the first high-side transistor, the second high-side transistor, and the second low-side transistor in the off state and drive the first low-side transistor between the on state and the off state.

6. The driver system of claim 5 , wherein:
wherein while the diagnostic circuit monitors the first charging voltage of the first voltage charging device and the second charging voltage of the second voltage charging device, the driver circuit is configured to generate one of the control signals as a varying drive signal and provide the varying drive signal to a control terminal of the first low-side transistor to drive the first low-side transistor between the on state and the off state.

7. The driver system of claim 6 , wherein the varying drive signal is a pulse-width modulation (PWM) drive signal.

8. The driver system of claim 6 , wherein the driver circuit is configured to start the varying drive signal at a start time, and wherein a charging of the first voltage charging device and a charging of the second voltage charging device start at the start time.

9. The driver system of claim 8 , wherein the diagnostic circuit is configured to determine the first charging time as a first duration from the start time to a first subsequent time at which the first charging voltage is charged to the first threshold voltage and determine the second charging time as a second duration from the start time to a second subsequent time at which the second charging voltage is charged to the second threshold voltage.

10. The driver system of claim 5 , wherein the driver circuit comprises:
a first driver configured to generate the control signals to drive the first high-side transistor and the first low-side transistor between respective switching states; and
a second driver configured to generate the control signals to drive the second high-side transistor and the second low-side transistor between respective switching states.

11. The driver system of claim 5 , wherein, while the first high-side transistor, the second high-side transistor, and the second low-side transistor are in the off state and while the first low-side transistor is driven between the on state and the off state, a first current is configured to flow from the first voltage charging device through the first output node, and through the first low-side transistor and a second current is configured to flow from the second voltage charging device, through the second output node, and through the first low-side transistor,
wherein under a normal operating condition, the second current is configured to flow from the second output node to the first low-side transistor through motor windings of the motor, and
wherein under a fault condition during which the short circuit condition is present, the second current is configured to flow from the second output node to the first low-side transistor via a short circuit.

12. The driver system of claim 1 , further comprising:
a driver circuit configured to generate control signals to drive the first high-side transistor, the first low-side transistor, the second high-side transistor, and the second low-side transistor between respective switching states, including at least an on state and an off state,
wherein while the diagnostic circuit monitors the first charging voltage of the first voltage charging device and the second charging voltage of the second voltage charging device, the driver circuit is configured to maintain the first high-side transistor, the second high-side transistor, and the second low-side transistor in an off state and drive the first low-side transistor between the on state and the off state,
wherein the diagnostic circuit is configured to detect a normal operating condition on a condition that the time difference between the first charging time and the second charging time is equal to or greater than the time difference threshold, and
wherein, on a condition that the diagnostic circuit detects the normal operating condition, the diagnostic circuit is configured to enable switching of the first high-side transistor and the second high-side transistor between respective switching states.

13. The driver system of claim 1 , wherein, on a condition that the diagnostic circuit detects the short circuit condition, the diagnostic circuit is configured to disable switching of the first high-side transistor and the second high-side transistor between respective switching states.

14. The driver system of claim 1 , wherein the diagnostic circuit includes a first comparator circuit configured to compare the first charging voltage to the first threshold voltage and generate a first comparison result and a second comparator circuit configured to compare the second charging voltage to the second threshold

Assignees

• Infineon Technologies Austria Ag

Inventors

• Qiu Yuqiang
• Tian Bin

Classifications

• H02J7/90 Primary

  Regulation of charging or discharging current or voltage · CPC title

• G01R31/52

  Testing for short-circuits, leakage current or ground faults · CPC title

• H02P27/08

  with pulse width modulation · CPC title

• H02M7/5387

  in a bridge configuration · CPC title

• H02M1/0003

  Details of control, feedback or regulation circuits · CPC title