Substrate processing and membrane release of transversely-excited film bulk acoustic resonator using a sacrificial tub

US12119805B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12119805-B2
Application numberUS-202117548234-A
CountryUS
Kind codeB2
Filing dateDec 10, 2021
Priority dateJun 15, 2018
Publication dateOct 15, 2024
Grant dateOct 15, 2024

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An acoustic resonator device is formed using a sacrificial layer and a front side etched cavity by forming a recess in a silicon substrate with a trap-rich top layer and filling the recess with sacrificial silicon nitride. A bonding oxide (BOX) layer is formed over the trap-rich layer and the sacrificial silicon nitride filled recess and a piezoelectric plate is bonded to the BOX layer. The sacrificial silicon nitride is then removed to form a cavity by using an etchant introduced through holes in the piezoelectric plate and BOX layer without removing the BOX layer from over the cavity.

First claim

Opening claim text (preview).

What is claimed: 1. A method of forming a filter device using a sacrificial layer and a front side etched cavity comprising: forming a recess in a silicon substrate with a trap-rich top layer; filling the recess with sacrificial silicon nitride; forming a bonding oxide (BOX) layer over the trap-rich layer and the sacrificial silicon nitride filled recess; bonding a piezoelectric plate to the BOX layer; and removing the sacrificial silicon nitride using an etchant introduced through holes in the piezoelectric plate and BOX layer to form a cavity without removing the BOX layer from over the cavity. 2. The method of claim 1 , wherein: forming the recess in the silicon substrate includes patterning the top of the trap-rich top layer and front side etching through the trap-rich top layer and into the substrate; and wherein removing the silicon nitride comprises using an isotropic Phosphoric acid etch through the holes to remove the silicon nitride but not the BOX layer. 3. The method of claim 1 , wherein removing the silicon nitride includes front side releasing a portion of the piezoelectric plate over the cavity to form a diaphragm spanning the cavity. 4. The method of claim 3 , further comprising: forming a conductor pattern on a front surface of the piezoelectric plate, wherein the conductor pattern includes an interdigital transducer (IDT) with interleaved fingers disposed on the diaphragm over the cavity; and forming a frontside dielectric on the front surface of the piezoelectric plate, wherein a thickness of the frontside dielectric is equal to a thickness of the BOX layer. 5. The method of claim 4 , wherein filling the recess includes depositing a blanket layer of silicon nitride material over the recess and trap-rich top layer, then polishing the blanket layer silicon nitride. 6. The method of claim 4 , wherein: the piezoelectric plate and the IDT are configured such that radio frequency signals applied to the IDT excite a primary shear acoustic mode in the piezoelectric plate over the cavity; and wherein a combined thickness of the diaphragm, of the frontside dielectric and of the BOX layer are selected to tune the primary shear acoustic modes in the piezoelectric plate. 7. The method of claim 4 , wherein the thickness of the frontside dielectric and the thickness of the BOX layer are each between 50-200 nm and a thickness of the piezoelectric plate is between 500 nm to 1000 nm; and wherein the thicknesses of the frontside dielectric and the thickness of the BOX layer are each less than half of thickness of the piezoelectric plate. 8. The method of claim 1 , wherein the substrate is Si, the BOX layer is SiO2, the IDT is metal, and the piezoelectric plate is one of lithium niobate or lithium tantalate; and wherein the cavity has a rectangular shape without a more shallow vertical depth in the center. 9. The method of claim 1 , wherein the substrate is a polymorphic or crystalline silicon (Si) material having a thickness of 250-500 um; the silicon nitride is a sacrificial tub having a predefined volume in the trap-rich layer and substrate, and has a thickness of between 1 and 10 μm thick; the BOX layer is an SiO 2 layer having a thickness of 50-200 nm; and the trap-rich layer is a polysilicon electrically insulating layer having a thickness of 1-10 um. 10. The method of claim 1 , wherein forming the recess includes patterning and etching an area of the trap-rich layer and substrate to a desired depth of the cavity; wherein forming the silicon nitride includes filling the recess with a sacrificial tub of material; and wherein removing the silicon nitride comprises etching away the sacrificial tub with a selective etchant that etches the sacrificial tub through the holes but does not etch the plate, the BOX layer or trap-rich layer. 11. A method of forming a filter device using a sacrificial layer and a front side etched cavity comprising: forming a recess in a silicon substrate; filling the recess with a sacrificial layer; forming a bonding oxide (BOX) layer over the substrate and the sacrificial layer filled in the recess; bonding a piezoelectric plate to the BOX layer; removing the sacrificial layer using an etchant introduced through holes in the piezoelectric plate and BOX layer to form a cavity without removing the BOX layer from over the cavity; and forming a frontside dielectric over the plate. 12. The method of claim 11 , wherein the front-side dielectric layer and the BOX layer are the same material, and a thickness tfd of the front-side dielectric layer and a thickness tbd of the BOX layer satisfy the relationship 0.5 tfd<tbd<1.5 tfd. 13. The method of claim 11 , wherein the front-side dielectric layer and the BOX layer are silicon dioxide dielectric layers; and tfd and tbd are 145 nm, or 0.326 times the thickness of the piezoelectric plate. 14. The method of claim 11 , wherein: forming the recess in the silicon substrate includes patterning a top of a trap-rich top layer of the substrate and front side etching through the trap-rich top layer and into the substrate; and wherein removing the sacrificial layer includes front side releasing a portion of the piezoelectric plate over the cavity to form a diaphragm spanning the cavity. 15. The method of claim 11 , further comprising: forming a conductor pattern on a front surface of the piezoelectric plate, wherein the conductor pattern includes an interdigital transducer (IDT) with interleaved fingers disposed on the diaphragm over the cavity. 16. The method of claim 15 , wherein the IDT fingers are aluminum and the front-side dielectric layer and BOX layer are silicon dioxide, and wherein a thickness tm of the fingers is equal to a thickness of the front-side dielectric layer which is equal to a thickness of the BOX layer. 17. A method of forming a filter device using a sacrificial layer and a front side etched cavity comprising: forming a recess in a silicon substrate; filling the recess with a sacrificial layer; forming a bonding oxide (BOX) layer over the substrate and on the sacrificial layer in the recess; bonding a piezoelectric plate to the BOX layer; forming a conductor pattern on a front surface of the piezoelectric plate, wherein the conductor pattern includes an interdigital transducer (IDT) with interleaved fingers disposed over the recess; removing the sacrificial layer using an etchant introduced through holes in the piezoelectric plate and BOX layer to form a cavity where the sacrificial layer was removed without removing the BOX layer from over the cavity; and forming a frontside dielectric over the plate. 18. The method of claim 17 , wherein forming the sacrificial layer includes blanket layer depositing silicon nitride material over the recess and substrate, then polishing the blanket layer silicon nitride. 19. The method of claim 17 , wherein: the piezoelectric plate and the IDT are configured such that radio frequency signals applied to the IDT excite a primary shear acoustic mode in the piezoelectric plate over the cavity; and wherein a combined thickness of the diaphragm, of the frontside dielectric and of the BOX layer are selected to tune the primary shear acoustic modes in the piezoelectric plate. 20. The method of claim 17 , wherein the thickness of the frontside dielectric and the thickness of the BOX layer are each between 50-200 nm and a thickness of the piezoelectric plate is between 500 nm to 1000 nm; and wherein the thicknesses of the frontside dielectric and the thickness of

Assignees

Inventors

Classifications

  • consisting of ceramic material (H03H9/177, H03H9/178 take precedence) · CPC title

  • the resonators or networks being of the membrane type · CPC title

  • consisting of a ladder configuration · CPC title

  • implemented with thin-film techniques · CPC title

  • comprising a ceramic piezoelectric layer · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12119805B2 cover?
An acoustic resonator device is formed using a sacrificial layer and a front side etched cavity by forming a recess in a silicon substrate with a trap-rich top layer and filling the recess with sacrificial silicon nitride. A bonding oxide (BOX) layer is formed over the trap-rich layer and the sacrificial silicon nitride filled recess and a piezoelectric plate is bonded to the BOX layer. The sac…
Who is the assignee on this patent?
Murata Manufacturing Co
What technology area does this patent fall under?
Primary CPC classification H03H9/02228. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 15 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).