Amplifier circuit and display apparatus having the same

Patent metadata

Field	Value
Publication number	US-12119795-B2
Application number	US-202318501389-A
Country	US
Kind code	B2
Filing date	Nov 3, 2023
Priority date	Jan 30, 2023
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

Disclosed is an amplifier circuit comprising a first stage having first and second input terminals, a second stage configured to amplify a voltage supplied from the first stage and including a pull-up node and a pull-down node, a third stage including an output terminal, a tenth PMOS transistor, and a tenth NMOS transistors having gate electrodes respectively connected to the pull-up node and the pull-down node of the second stage, the third stage configured to perform a pull-up driving and pull-down driving of the amplified voltage, a first boosting circuit including an eleventh PMOS transistor having a gate electrode connected to the pull-up node and the first boosting circuit configured to increase a current in the first stage, and a second boosting circuit including an eleventh NMOS transistor having a gate electrode connected to the pull-down node and configured to increase the current in the first stage.

First claim

What is claimed is:

1. An amplifier circuit comprising:
a first stage including a first input terminal and a second input terminal, the first stage configured to supply a voltage;
a second stage connected to the first stage and configured to amplify the voltage supplied from the first stage, the second stage including a pull-up node and a pull-down node;
a third stage including an output terminal, a tenth PMOS transistor having a gate electrode connected to the pull-up node of the second stage, and a tenth NMOS transistor having a gate electrode connected to the pull-down node of the second stage, the third stage configured to perform a pull-up driving of the amplified voltage supplied from the second stage or a pull-down driving of the amplified voltage supplied from the second stage;
a first boosting circuit including an eleventh PMOS transistor having a gate electrode connected to the pull-up node included the second stage and the gate electrode of the tenth PMOS transistor included in the third stage, the first boosting circuit configured to increase a current in the first stage while the eleventh PMOS transistor is turned on; and
a second boosting circuit including an eleventh NMOS transistor having a gate electrode connected to the pull-down node included the second stage and the gate electrode of the tenth NMOS transistor included in the third stage, the second boosting circuit configured to increase the current in the first stage while the eleventh NMOS transistor is turned on.

2. The amplifier circuit according to claim 1 , wherein the first stage further includes:
a first PMOS transistor including a gate electrode connected to a direct current (DC) voltage;
a first NMOS transistor including a gate electrode connected to the DC voltage;
a second PMOS transistor having a gate electrode connected to the first input terminal;
a second NMOS transistor having a gate electrode connected to the first input terminal;
a third PMOS transistor having a gate electrode connected to the second input terminal; and
a third NMOS transistor having a gate electrode connected to the second input terminal,
wherein the first input terminal of the first stage is connected to the output terminal of the third stage.

3. The amplifier circuit according to claim 2 , wherein a drain electrode of the eleventh PMOS transistor is connected to a source electrode of the second PMOS transistor and a source electrode of the third PMOS transistor, and a drain electrode of the eleventh NMOS transistor is connected to a source electrode of the second NMOS transistor and a source electrode of the third NMOS transistor.

4. The amplifier circuit according to claim 3 , wherein the second stage further includes:
a fourth PMOS transistor having a gate electrode connected to a PMOS feedback node;
a fifth PMOS transistor having a gate electrode connected to the PMOS feedback node;
a fourth NMOS transistor having a gate electrode connected to a NMOS feedback node; and
a fifth NMOS transistor having a gate electrode connected to the NMOS feedback node.

5. The amplifier circuit according to claim 4 , wherein the first boosting circuit further includes a twelfth PMOS transistor having a gate electrode connected to the PMOS feedback node, and the second boosting circuit further includes a twelfth NMOS transistor having a gate electrode connected to the NMOS feedback node.

6. The amplifier circuit according to claim 5 , wherein a drain electrode of the twelfth PMOS transistor is connected to the source electrode of the second PMOS transistor and the source electrode of the third PMOS transistor, and a drain electrode of the twelfth NMOS transistor is connected to the source electrode of the second NMOS transistor and the second electrode of the third NMOS transistor.

7. The amplifier circuit according to claim 5 , wherein the first boosting circuit further includes a thirteenth PMOS transistor having a gate electrode connected to pull-up node and a fourteenth PMOS transistor having a gate electrode connected to the pull-up node, and the second boosting circuit further includes a thirteenth NMOS transistor having a gate electrode connected to the pull-down node and a fourteenth NMOS transistor having a gate electrode connected to the pull-down node.

8. The amplifier circuit according to claim 7 , wherein a drain electrode of the thirteenth PMOS transistor is connected to a drain electrode of the third NMOS transistor, a drain electrode of the fourteenth PMOS transistor is connected to a drain electrode of the second NMOS transistor, a drain electrode of the thirteenth NMOS transistor is connected to a drain electrode of the second PMOS transistor, and a drain electrode of the fourteenth NMOS transistor is connected to a drain electrode of the third PMOS transistor.

9. The amplifier circuit according to claim 1 , wherein the amplifier circuit is a unity gain buffer.

10. A display apparatus comprising:
a display panel including a plurality of pixels, a plurality of gate lines connected to the plurality of pixels, and a plurality of data lines connected to the plurality of pixels;
a gate driver configured to drive the plurality of gate lines of the display panel; and
a data driver configured to drive the plurality of data lines of the display panel, the data driver including an amplifier circuit that amplifies a data voltage, the amplifier circuit including:
a first stage including a first input terminal and a second input terminal, the first input terminal connected to an output terminal of the amplifier circuit that outputs the data voltage;
a second stage connected to the first stage and configured to amplify the data voltage, the second stage including a pull-up node and a pull-down node;
a third stage including the output terminal of the amplifier circuit that is connected to the first input terminal of the first stage, a pull-up PMOS transistor having a gate electrode connected to the pull-up node of the second stage, a pull-down NMOS transistor having a gate electrode connected to the pull-down node of the second stage, the third stage configured to perform a pull-up driving of the amplified data voltage supplied from the second stage while the pull-up PMOS transistor is turned on or a pull-down driving of the amplified data voltage supplied from the second stage while the pull-down NMOS transistor is turned on;
a first boosting circuit including a first boosting PMOS transistor having a gate electrode connected to the pull-up node included in the second stage and the gate electrode of the pull-up PMOS transistor included in the third stage, the first boosting circuit configured to increase a current in the first stage while the first boosting PMOS transistor is turned on; and
a second boosting circuit including a first boosting NMOS transistor having a gate electrode connected to the pull-down node included the second stage and the gate electrode of the pull-down NMOS transistor included in the third stage, the second boosting circuit configured to increase the current in the first stage while the first boosting NMOS transistor is turned on.

11. The display apparatus according to claim 10 , wherein the amplifier circuit is a unity gain buffer.

12. The display apparatus according to claim 10 , wherein the first boosting circuit and the second boosting circuit are included in the first stage.

13. The display apparatus according to claim 10 , wherein the first stage further includes:
a first PMOS transistor including a gate electrode connected to a direct current (DC) voltage;
a first NMOS transistor including a gate electrode connected to the DC voltage;
a second PMOS tran

Assignees

• Lg Display Co Ltd

Inventors

• Lee Hongju
• Kim Hyunwoo
• Kim Beom-Jin

Classifications

• G09G2310/0243

  Details of the generation of driving signals · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G3/3275 Primary

  Details of drivers for data electrodes · CPC title

• H03F1/0205 Primary

  in transistor amplifiers · CPC title