Beamformer integrated circuits with multiple-stage hybrid splitter/combiner circuits

US12119533B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12119533-B2
Application numberUS-202117457472-A
CountryUS
Kind codeB2
Filing dateDec 15, 2021
Priority dateDec 15, 2021
Publication dateOct 15, 2024
Grant dateOct 15, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A multiple-stage splitter/combiner circuit includes first and second splitter/combiner circuits coupled together. The first splitter/combiner circuit has first, second, and third input/output (I/O) ports, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with first and second terminals coupled to the second and third I/O ports, respectively. The second splitter/combiner circuit has fourth, fifth, and sixth I/O ports, and a ring of multiple quarter wave lines, which includes third and fourth quarter wave lines. The third and fourth quarter wave lines each extend from the fourth I/O port in different directions from each other to the fifth and sixth I/O ports, respectively.

First claim

Opening claim text (preview).

What is claimed is: 1. A multiple-stage splitter/combiner circuit comprising: a first splitter/combiner circuit with a first input/output (I/O) port, a second I/O port, a third I/O port, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with a first terminal coupled to the second I/O port and a second terminal coupled to the third I/O port; and a second splitter/combiner circuit coupled to the first splitter/combiner circuit, wherein the second splitter/combiner circuit includes a fourth I/O port connected to the second I/O port, a fifth I/O port, a sixth I/O port, and a ring of multiple quarter wave lines that includes a third quarter wave line with a first end coupled to the fourth I/O port and a second end coupled to the fifth I/O port, a fourth quarter wave line with a first end coupled to the fourth I/O port and a second end coupled to the sixth I/O port, a fifth quarter wave line with a first end coupled to the fifth I/O port, and a sixth quarter wave line with a first end coupled to the sixth I/O port and a second end coupled to a second end of the fifth quarter wave line, wherein the third quarter wave line and the fourth quarter wave line extend from the fourth I/O port in different directions from each other. 2. A multiple-stage splitter/combiner circuit comprising: a first splitter/combiner circuit with a first input/output (I/O) port, a second I/O port, a third I/O port, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with a first terminal coupled to the second I/O port and a second terminal coupled to the third I/O port; and a second splitter/combiner circuit coupled to the first splitter/combiner circuit, wherein the second splitter/combiner circuit includes a fourth I/O port, a fifth I/O port, a sixth I/O port, and a ring of multiple quarter wave lines that includes a third quarter wave line with a first end coupled to the fourth I/O port and a second end coupled to the fifth I/O port, a fourth quarter wave line with a first end coupled to the fourth I/O port and a second end coupled to the sixth I/O port, a fifth quarter wave line with a first end coupled to the fifth I/O port, and a sixth quarter wave line with a first end coupled to the sixth I/O port and a second end coupled to a second end of the fifth quarter wave line, wherein the third quarter wave line and the fourth quarter wave line extend from the fourth I/O port in different directions from each other, and wherein the first and second quarter wave lines extend in parallel with each other so that the second I/O port and the third I/O port are physically separated by a distance of about a width of the first resistor. 3. The multiple-stage splitter/combiner circuit of claim 1 , wherein the third quarter wave line and the fourth quarter wave line extend from the fourth I/O port in opposite directions from each other so that the fifth I/O port and the sixth I/O port are physically separated by a distance equal to a combined length of the third and fourth quarter wave lines. 4. The multiple-stage splitter/combiner circuit of claim 1 , wherein: the first splitter/combiner circuit is a first-stage splitter/combiner circuit; the second splitter/combiner circuit is a second-stage splitter/combiner circuit; and the second I/O port is coupled to the fourth I/O port. 5. The multiple-stage splitter/combiner circuit of claim 4 , further comprising: a third splitter/combiner circuit coupled to the first splitter/combiner circuit, wherein the third splitter/combiner circuit includes a seventh I/O port, an eighth I/O port, a ninth I/O port, and a second ring of multiple quarter wave lines that includes a seventh quarter wave line with a first end coupled to the seventh I/O port and a second end coupled to the eighth I/O port, an eighth quarter wave line with a first end coupled to the seventh I/O port and a second end coupled to the ninth I/O port, a ninth quarter wave line with a first end coupled to the eighth I/O port, and a tenth quarter wave line with a first end coupled to the ninth I/O port and a second end coupled to a second end of the ninth quarter wave line, wherein the seventh quarter wave line and the eighth quarter wave line extend from the seventh I/O port in different directions from each other. 6. The multiple-stage splitter/combiner circuit of claim 1 , wherein: the second splitter/combiner circuit is a first-stage splitter/combiner circuit; the first splitter/combiner circuit is a second-stage splitter/combiner circuit; and the first I/O port is coupled to the fifth I/O port. 7. The multiple-stage splitter/combiner circuit of claim 6 , further comprising: a third splitter/combiner circuit coupled to the second splitter/combiner circuit, wherein the third splitter/combiner circuit includes a seventh I/O port, an eighth I/O port, a ninth I/O port, a seventh quarter wave line with a first end coupled to the seventh I/O port and a second end coupled to the eighth I/O port, an eighth quarter wave line with a first end coupled to the seventh I/O port and a second end coupled to the ninth I/O port, and a second resistor with a first terminal coupled to the seventh I/O port and a second terminal coupled to the eighth I/O port. 8. A multiple-stage splitter/combiner circuit comprising: a first splitter/combiner circuit with a first input/output (I/O) port, a second I/O port, a third I/O port, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O port and a second end coupled to the third I/O port, and a first resistor with a first terminal coupled to the second I/O port and a second terminal coupled to the third I/O port; and a second splitter/combiner circuit coupled to the first splitter/combiner circuit, wherein the second splitter/combiner circuit includes a fourth I/O port, a fifth I/O port, a sixth I/O port, and a ring of multiple quarter wave lines that includes a third quarter wave line with a first end coupled to the fourth I/O port and a second end coupled to the fifth I/O port, a fourth quarter wave line with a first end coupled to the fourth I/O port and a second end coupled to the sixth I/O port, a fifth quarter wave line with a first end coupled to the fifth I/O port, and a sixth quarter wave line with a first end coupled to the sixth I/O port and a second end coupled to a second end of the fifth quarter wave line, wherein the third quarter wave line and the fourth quarter wave line extend from the fourth I/O port in different directions from each other, and wherein the first, second, third, fourth, fifth, and sixth quarter wave lines each include an unbalanced transmission line. 9. The multiple-stage splitter/combiner circuit of claim 8 , wherein the second splitter/combiner circuit further comprises: a first port coupled to the second end of the fifth quarter wave line; a second port coupled to the second end of the sixth quarter wave line; a seventh quarter wave line coupled between the first port and a conductive node; an eighth quarter wave line coupled between the second port and the conductive node; a second resistor coupled between the first port and a ground reference; and a third resistor coupled between the second port and the ground reference. 10. A mul

Assignees

Inventors

Classifications

  • Circuits · CPC title

  • the phase-shifters being digital · CPC title

  • Stripline fed arrays (H01Q21/065 takes precedence) · CPC title

  • for beam forming · CPC title

  • H01P5/16Primary

    Conjugate devices, i.e. devices having at least one port decoupled from one other port · CPC title

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What does patent US12119533B2 cover?
A multiple-stage splitter/combiner circuit includes first and second splitter/combiner circuits coupled together. The first splitter/combiner circuit has first, second, and third input/output (I/O) ports, a first quarter wave line with a first end coupled to the first I/O port and a second end coupled to the second I/O port, a second quarter wave line with a first end coupled to the first I/O p…
Who is the assignee on this patent?
Nxp Bv, Npx B V
What technology area does this patent fall under?
Primary CPC classification H01P5/16. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 15 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).