Imaging device

Patent metadata

Field	Value
Publication number	US-12119359-B2
Application number	US-201917292258-A
Country	US
Kind code	B2
Filing date	Dec 6, 2019
Priority date	Dec 20, 2018
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

An imaging device according to an embodiment of the present disclosure includes: a first substrate including, in a first semiconductor substrate, a sensor pixel that performs photoelectric conversion; a second substrate including, in a second semiconductor substrate, a readout circuit that outputs a pixel signal based on charges outputted from the sensor pixel, in which the second substrate is stacked on the first substrate; and a first hydrogen diffusion prevention layer provided between the first semiconductor substrate and the second semiconductor substrate.

First claim

The invention claimed is:

1. An imaging device comprising:
a first substrate including, in a first semiconductor substrate, a sensor pixel that performs photoelectric conversion, and the first semiconductor substrate defines a first surface and a second surface such that the first surface is opposite the second surface;
a second substrate including, in a second semiconductor substrate, a readout circuit that outputs a pixel signal based on charges outputted from the sensor pixel, the second substrate being stacked on the first substrate, such that the second substrate is opposed to the first surface of the first semiconductor substrate;
a first hydrogen diffusion prevention layer abutting the first surface, disposed between the first semiconductor substrate and the second semiconductor substrate; and
a second hydrogen diffusion prevention layer abutting the second surface.

2. The imaging device according to claim 1 , wherein the first hydrogen diffusion prevention layer has a film density in a range from 2.7 g/cm to 3.5 g/cm.

3. The imaging device according to claim 1 , wherein a stacked body including the first substrate and the second substrate further includes a hydrogen supplying layer on side closer to the second substrate than the first hydrogen diffusion prevention layer.

4. The imaging device according to claim 1 , wherein
a stacked body including the first substrate and the second substrate includes, between the first semiconductor substrate and the second semiconductor substrate, an interlayer insulating film and a first through-wiring line provided inside the interlayer insulating film, and
the first substrate and the second substrate are electrically coupled to each other by the first through-wiring line.

5. The imaging device according to claim 4 , wherein the first through-wiring line includes a metal layer between the first through-wiring line and the interlayer insulating film, the metal layer including a metal having an oxygen absorption effect.

6. The imaging device according to claim 1 , wherein the first substrate further includes a logic circuit that processes the pixel signal.

7. The imaging device according to claim 1 , wherein
the sensor pixel includes a photoelectric conversion element, a transfer transistor electrically coupled to the photoelectric conversion element, and a floating diffusion that temporarily holds charges outputted from the photoelectric conversion element via the transfer transistor, and
the readout circuit includes a reset transistor that resets an electric potential of the floating diffusion to a predetermined electric potential, an amplification transistor that generates, as the pixel signal, a signal of a voltage corresponding to a level of the charges held in the floating diffusion, and a selection transistor that controls an output timing of the pixel signal from the amplification transistor.

8. The imaging device according to claim 7 , wherein
the first substrate includes, on side of one surface of the first semiconductor substrate opposed to the second substrate, the photoelectric conversion element, the transfer transistor, and the floating diffusion, and
the second substrate includes the readout circuit on side of one surface of the second semiconductor substrate, and is attached to the first substrate, with another surface, opposed to the one surface, of the second semiconductor substrate being opposed to the side of the one surface of the first semiconductor substrate.

9. The imaging device according to claim 8 , wherein the one surface of the first semiconductor substrate and the one surface of the second semiconductor substrate have mutually different interface state densities.

10. The imaging device according to claim 1 , further comprising a third substrate including, in a third semiconductor substrate, a logic circuit that processes the pixel signal, wherein
the first substrate, the second substrate, and the third substrate are stacked in this order.

11. The imaging device according to claim 10 , wherein
the second substrate and the third substrate are electrically coupled to each other by a junction between pad electrodes in a case where the second substrate and the third substrate include the respective pad electrodes, and
the second substrate and the third substrate are electrically coupled to each other by a second through-wiring line penetrating the third semiconductor substrate in a case where the third substrate includes the second through-wiring line.

12. The imaging device according to claim 8 , further comprising a third substrate including, in a third semiconductor substrate, a logic circuit that processes the pixel signal, wherein
the third substrate includes the logic circuit on side of one surface of the third semiconductor substrate, and is attached to the second substrate, with another surface, opposed to the one surface, of the third semiconductor substrate being opposed to the side of the one surface of the second semiconductor substrate.

13. The imaging device according to claim 12 , wherein the logic circuit includes a silicide on a front surface of an impurity diffusion region in contact with a source electrode or a drain electrode.

14. The imaging device according to claim 11 , wherein
the sensor pixel includes a photoelectric conversion element, a transfer transistor electrically coupled to the photoelectric conversion element, and a floating diffusion that temporarily holds charges outputted from the photoelectric conversion element via the transfer transistor,
the readout circuit includes a reset transistor that resets an electric potential of the floating diffusion to a predetermined electric potential, an amplification transistor that generates, as the pixel signal, a signal of a voltage corresponding to a level of the charges held in the floating diffusion, and a selection transistor that controls an output timing of the pixel signal from the amplification transistor,
a stacked body including the first substrate and the second substrate includes, between the first semiconductor substrate and the second semiconductor substrate, an interlayer insulating film and a first through-wiring line provided inside the interlayer insulating film, and
a gate of the transfer transistor is electrically coupled to the logic circuit via the first through-wiring line and the pad electrodes or the second through-wiring line.

15. The imaging device according to claim 12 , comprising an interlayer insulating film between the first semiconductor substrate and the second semiconductor substrate, wherein
the first substrate further includes, inside the interlayer insulating film, a gate wiring line extending in a direction parallel to the first substrate, and
a gate of the transfer transistor is electrically coupled to the logic circuit via the gate wiring line.

16. The imaging device according to claim 14 , wherein
the second substrate includes the readout circuit for every four of the sensor pixels, and
a plurality of the first through-wiring lines are arranged side by side in a strip shape in a first direction in a plane of the first substrate.

17. The imaging device according to claim 16 , wherein the sensor pixels are arranged in matrix in the first direction and a second direction orthogonal to the first direction, and
the second substrate further includes
a first control line electrically coupled to the gate of the transfer transistor of each of the sensor pixels arranged side by side in the second direction,
a second control line electrically coupled to a gate of each of the

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Baba Koichi

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/0253

  comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title