Pixel circuit and driving method thereof, and display panel

US12118938B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12118938-B2
Application numberUS-202318240713-A
CountryUS
Kind codeB2
Filing dateAug 31, 2023
Priority dateNov 25, 2021
Publication dateOct 15, 2024
Grant dateOct 15, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes a drive module, a data write module, an auxiliary module, a compensation module, a storage module, a coupling module, and a light-emitting module. The data write module is configured to write a data-voltage-related voltage to a control terminal of the drive module through the auxiliary module. The compensation module is connected between a first terminal of the drive module and the control terminal of the drive module and is configured to compensate for the threshold voltage of the drive module. The coupling module is connected to the compensation module and is configured to adjust the voltage at the control terminal of the drive module according to a received jump voltage by using the compensation module. The storage module is connected to the control terminal of the drive module.

First claim

Opening claim text (preview).

What is claimed is: 1. A pixel circuit, comprising a drive module, a data write module, an auxiliary module, a compensation module, a storage module, a coupling module, and a light-emitting module, wherein the data write module is configured to write a data-voltage-related voltage to a control terminal of the drive module through the auxiliary module; the compensation module is connected between a first terminal of the drive module and the control terminal of the drive module and is configured to compensate for a threshold voltage of the drive module; the coupling module is connected to the compensation module and is configured to adjust a voltage at the control terminal of the drive module according to a received jump voltage through the compensation module; the storage module is connected to the control terminal of the drive module and is configured to store the voltage at the control terminal of the drive module; and the drive module is configured to provide a drive signal to the light-emitting module according to the voltage at the control terminal to drive the light-emitting module to emit light. 2. The pixel circuit of claim 1 , wherein the storage module comprises a first capacitor, wherein a first electrode of the first capacitor is connected to a fixed voltage, and a second electrode of the first capacitor is connected to the control terminal of the drive module. 3. The pixel circuit of claim 1 , wherein the auxiliary module comprises a first transistor, wherein a gate of the first transistor is connected to a first scan line, a first electrode of the first transistor is connected to a second terminal of the data write module, a second electrode of the first transistor is connected to a second terminal of the drive module, and a first terminal of the data write module is connected to a data line. 4. The pixel circuit of claim 1 , wherein the auxiliary module comprises a first transistor and a second capacitor, wherein a gate of the first transistor is connected to a first scan line, a first electrode of the first transistor is connected to a second terminal of the data write module, a second electrode of the first transistor is connected to a second terminal of the drive module, a first terminal of the data write module is connected to a data line, a first terminal of the second capacitor is connected to a fixed voltage, and a second terminal of the second capacitor is connected to the first electrode of the first transistor or the second electrode of the first transistor. 5. The pixel circuit of claim 1 , wherein the compensation module comprises a second transistor, wherein the second transistor is a double-gate transistor that comprises a first sub-transistor and a second sub-transistor, wherein a gate of the first sub-transistor and a gate of the second sub-transistor are each connected to a first scan line, a first electrode of the first sub-transistor is connected to the first terminal of the drive module, a second electrode of the first sub-transistor is connected to a first electrode of the second sub-transistor, and a second electrode of the second sub-transistor is connected to the control terminal of the drive module. 6. The pixel circuit of claim 5 , wherein the jump voltage is a pulse voltage, the coupling module comprises a third capacitor, a first electrode of the third capacitor is connected to the pulse voltage, and a second electrode of the third capacitor is connected to the first electrode of the second sub-transistor. 7. The pixel circuit of claim 1 , wherein the compensation module comprises a second transistor, wherein the second transistor is a tri-gate transistor that comprises a first sub-transistor, a second sub-transistor, and a third sub-transistor, wherein a gate of the first sub-transistor, a gate of the second sub-transistor, and a gate of the third sub-transistor are each connected to a first scan line, a first electrode of the first sub-transistor is connected to the first terminal of the drive module, a second electrode of the first sub-transistor is connected to a first electrode of the second sub-transistor, a second electrode of the second sub-transistor is connected to a first electrode of the third sub-transistor, and a second electrode of the third sub-transistor is connected to the control terminal of the drive module. 8. The pixel circuit of claim 7 , wherein the coupling module is configured to couple the jump voltage to at least one of the first electrode of the second sub-transistor or the second electrode of the second sub-transistor. 9. The pixel circuit of claim 8 , wherein the jump voltage is a pulse voltage, and the coupling module comprises a third capacitor and a fourth capacitor, wherein a first electrode of the third capacitor is connected to the pulse voltage, a second electrode of the third capacitor is connected to the second electrode of the second sub-transistor, a first electrode of the fourth capacitor is connected to the pulse voltage or a fixed voltage, and a second electrode of the fourth capacitor is connected to the first electrode of the second sub-transistor. 10. The pixel circuit of claim 1 , wherein the compensation module comprises a second transistor, wherein the second transistor is a four-gate transistor that comprises a first sub-transistor, a second sub-transistor, a third sub-transistor, and a fourth sub-transistor, wherein a gate of the first sub-transistor, a gate of the second sub-transistor, a gate of the third sub-transistor, and a gate of the fourth sub-transistor are each connected to a first scan line, a first electrode of the first sub-transistor is connected to the first terminal of the drive module, a second electrode of the first sub-transistor is connected to a first electrode of the second sub-transistor, a second electrode of the second sub-transistor is connected to a first electrode of the third sub-transistor, a second electrode of the third sub-transistor is connected to a first electrode of the fourth sub-transistor, and a second electrode of the fourth sub-transistor is connected to the control terminal of the drive module; and the coupling module is configured to couple the jump voltage to at least one of the first electrode of the second sub-transistor, the second electrode of the second sub-transistor, or the second electrode of the third sub-transistor. 11. The pixel circuit of claim 10 , wherein the jump voltage is a pulse voltage, and the coupling module comprises a third capacitor, a fourth capacitor, and a fifth capacitor, wherein a first electrode of the third capacitor is connected to the pulse voltage, a second electrode of the third capacitor is connected to the second electrode of the third sub-transistor, a first electrode of the fourth capacitor is connected to the pulse voltage or a fixed voltage, a second electrode of the fourth capacitor is connected to the second electrode of the second sub-transistor, a first electrode of the fifth capacitor is connected to the pulse voltage or a fixed voltage, and a second electrode of the fifth capacitor is connected to the second electrode of the first sub-transistor. 12. The pixel circuit of claim 6 , wherein a pulse of the pulse voltage is after a pulse signal transmitted on the first scan line. 13. The pixel circuit of claim 12 , wherein the pulse voltage jumps from a high level to a low level after the compensation module is turned off and jumps from a low level to a high level before the light-emitting module emits light; or the pulse voltage jumps from a low level to a high level after the compensation module is turned off and jumps from a high level to a low level before the light-emitting module em

Assignees

Inventors

Classifications

  • Improving the luminance or brightness uniformity across the screen · CPC title

  • Details of timing specific for flat panels, other than clock recovery · CPC title

  • with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

  • being a dynamic memory with more than one capacitor · CPC title

  • used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

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What does patent US12118938B2 cover?
A pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes a drive module, a data write module, an auxiliary module, a compensation module, a storage module, a coupling module, and a light-emitting module. The data write module is configured to write a data-voltage-related voltage to a control terminal of the drive module through the auxiliary module. The compens…
Who is the assignee on this patent?
Yungu Guan Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3233. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 15 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 10 related publications on this page (citations in our corpus or others sharing the same primary CPC).