Bias unit element with binary weighted charge transfer lines

Patent metadata

Field	Value
Publication number	US-12118331-B2
Application number	US-202117163588-A
Country	US
Kind code	B2
Filing date	Feb 1, 2021
Priority date	Feb 1, 2021
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

A Bias Unit Element (UE) comprises NAND gates with complementary outputs, the complementary outputs coupled through a charge transfer capacitor to a differential charge transfer bus comprising positive charge transfer lines and negative charge transfer lines. Each line of the differential charge transfer bus has a particular binary weighted line weight, such as 1, 2, 4, 2, 4, 8, and 4, 8, 16. Digital bias inputs are provided to the Bias UE NAND gate inputs, with a clear bit to initialize charge, and a sign input for enabling one of a positive Bias UE or negative Bias UE. A low-to-high transition causes a transfer of charge to the binary weighted charge transfer bus, thereby adding or subtracting a bias value from the charge transfer bus.

First claim

We claim:

1. A Bias Unit Element (UE) receiving an E digital input with an enable bit and generating charge coupled to a charge transfer bus comprising charge transfer lines, each charge transfer line having an associated weight, the Bias UE comprising:
a plurality of logic gates, each logic gate having an input coupled to an E digital input bit and the enable bit and generating a positive output and a negative output;
the positive output coupled through a first charge transfer capacitor to a positive charge transfer line, the negative output coupled through a second charge transfer capacitor to a negative charge transfer line;
each charge transfer line having an associated binary weight, the binary weight for each charge transfer line including at least weights 1, 2, 4, 8, and 16.

2. The Bias UE of claim 1 where each logic gate comprises a NAND gate having an input coupled to an E digital bit, an input coupled to the enable bit, an output coupled to the negative output and also to an inverter generating the positive output.

3. The Bias UE of claim 1 where an E[0] bit is coupled to the input of a logic gate of the plurality of logic gates and the positive output is coupled through a different first charge transfer capacitor to a negative charge transfer line with weight 1, and the negative output is coupled through a different second charge transfer capacitor to a positive charge transfer line with weight 1.

4. The Bias UE of claim 1 where an E[1] bit is coupled to the input of a logic gate of the plurality of logic gates and the positive output is coupled through a different first charge transfer capacitor to a negative charge transfer line with weight 2, and the negative output is coupled through a different second charge transfer capacitor to a positive charge transfer line with weight 2.

5. The Bias UE of claim 1 where an E[2] bit is coupled to the input of a logic gate of the plurality of logic gates and the positive output is coupled through a different first charge transfer capacitor to a negative charge transfer line with weight 4, and the negative output is coupled through a different second charge transfer capacitor to a positive charge transfer line with weight 4.

6. The Bias UE of claim 1 where an E[3] bit is coupled to the input of a logic gate of the plurality of logic gates and the positive output is coupled through a different first charge transfer capacitor to a negative charge transfer line with weight 8, and the negative output is coupled through a different second charge transfer capacitor to a positive charge transfer line with weight 8.

7. The Bias UE of claim 1 where an E[4] bit is coupled to the input of a logic gate of the plurality of logic gates and the positive output is coupled through a different first charge transfer capacitor to a negative charge transfer line with weight 16, and the negative output is coupled through a different second charge transfer capacitor to a positive charge transfer line with weight 16.

8. The Bias UE of claim 1 where an E[5] bit is coupled to the input of a logic gate of the plurality of logic gates and the positive output is coupled through different charge transfer capacitors to negative charge transfer lines with weights 2, 4, 4, and 8; and the negative output is coupled through different charge transfer capacitors to positive charge transfer lines with weights 2, 4, 4, and 8.

9. A Bias Unit Element (UE) receiving a digital E input, a sign bit, and transferring a bias value to a differential charge transfer bus, the Bias UE comprising:
the differential charge transfer bus comprising a plurality of positive charge transfer lines and a plurality of negative charge transfer lines;
a positive bias UE enabled when the sign bit is positive, the positive bias UE comprising a plurality of logic gates generating a positive output and a negative output from each E input bit, each positive output coupled through a unique first charge transfer capacitor to a negative charge transfer line, and each negative output coupled through a unique second charge transfer capacitor to a positive charge transfer line;
a negative bias UE enabled when the sign bit is negative, the negative bias UE comprising a plurality of logic gates generating a positive output and a negative output from each E input bit, each positive output coupled through a first charge transfer capacitor to a positive charge transfer line, and each negative output coupled through a second charge transfer capacitor to a negative charge transfer line.

10. The Bias UE of claim 9 where the positive charge transfer lines and the negative charge transfer lines each have weights 1, 2, 4, 8, and 16.

11. The Bias UE of claim 9 where the plurality of logic gates of the positive bias UE comprises a NAND gate having an input coupled to a respective E digital input bit and input coupled to the sign bit either with or without an inversion, the NAND gate output generating the positive output, the NAND gate output coupled to an inverter generating the negative output.

12. The Bias UE of claim 9 where an active E[0] bit of the input causes charge to be added to or subtracted from at least one of a positive charge transfer line or negative charge transfer line with weight 1.

13. The Bias UE of claim 9 where an active E[1] bit of the input causes charge to be added or subtracted from at least one of a positive charge transfer line or negative charge transfer line with weight 2.

14. The Bias UE of claim 9 where an active E[2] bit of the input causes charge to be added or subtracted from at least one of a positive charge transfer line or negative charge transfer line with weight 4.

15. The Bias UE of claim 9 where an active E[3] bit of the input causes charge to be added or subtracted from at least one of a positive charge transfer line or negative charge transfer line with weight 8.

16. The Bias UE of claim 9 where an active E[4] bit of the input causes charge to be added or subtracted from at least one of a positive charge transfer line or negative charge transfer line with weight 16.

17. The Bias UE of claim 9 where an active E[5] bit of the input causes charge to be added or subtracted from at least one of a positive charge transfer line or negative charge transfer line with weights 2, 4, 4, and 8.

18. The Bias UE of claim 9 where the positive charge transfer lines and negative charge transfer lines each have weights 1, 2, 4, 8, and 16.

19. A Bias Unit Element (UE) receiving a digital bias value E, a clear bit input, and a sign bit input, the Bias UE generating a bias charge coupled to a differential charge transfer bus in response to the digital bias value E, the Bias UE comprising:
a positive Bias UE enabled when the sign bit input is positive;
a negative Bias UE enabled when the sign bit input is negative;
the positive bias UE comprising a plurality of logic gates, each logic gate coupled to one of the digital bias E bits, the sign bit input, and the clear bit input, each logic gate generating a positive output and a negative output which is the complement of the positive output, each positive output of each of the plurality of logic gates coupled through a charge transfer capacitor to a respective negative charge transfer line and each negative output of each of the plurality of logic gates coupled through a charge transfer capacitor to a respective positive charge transfer line;
the negative bias UE comprising a plurality of logic gates, each logic gate coupled to one of the digital bias E bits, the sign bit input, and the clear bit i

Assignees

• Ceremorphic Inc

Inventors

• Kraemer Martin
• Boesch Ryan
• Xiong Wei

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• H03M1/38

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• G06F2207/4814

  Non-logic devices, e.g. operational amplifiers · CPC title