Removal of hardware intellectual property and programmable replacement

Patent metadata

Field	Value
Publication number	US-12118282-B2
Application number	US-202117551318-A
Country	US
Kind code	B2
Filing date	Dec 15, 2021
Priority date	Dec 21, 2020
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

In general, embodiments of the present disclosure provide methods, apparatus, systems, computer program products, computing devices, computing entities, and/or the like for altering a design of a hardware intellectual property (IP). In accordance with various embodiments, a representation of the design of the hardware IP is converted to generate a control and data flow graph (CDFG) for the design. An entropy analysis of the CDFG is conducted to identify one or more control paths and/or data paths for removal. Responsive to identifying control path(s) for removal, control logic for the control path(s) is removed from the design and replaced with first reconfigurable logic. Responsive to identifying data path(s) for removal, datapath logic for the data path(s) is removed from the design and replaced with second reconfigurable logic. Logic synthesis is then performed on the design, along with verification to check functional correctness of the design of the hardware.

First claim

The invention claimed is:

1. A computer-implemented method comprising:
generating, using one or more processors, a control and data flow graph (CDFG) representing a hardware IP design, the CDFG comprising a plurality of control paths and/or data paths;
performing, using the one or more processors, an entropy analysis of the CDFG to determine an entropy measure for each of the plurality of control paths and/or data paths, the entropy measure representing a complexity of an associated control path or an associated data path;
identifying, using the one or more processors, a subset of control paths and/or data paths for removal from the hardware IP design based at least in part on the entropy measure for each of the plurality of control paths and/or data paths;
generating, using the one or more processors, a reduced design based at least in part on: (i) replacing control logic of the hardware IP design represented by each control path of the subset of control paths and/or data paths for removal with first reconfigurable logic, and (ii) replacing data path logic of the hardware IP design represented by each data path of the subset of control paths and/or data paths with second reconfigurable logic; and
providing, using the one or more processors, access to the reduced design.

2. The method of claim 1 , wherein access to the reduced design is provided in accordance with a determination that the reduced design is functionally correct with respect to the hardware IP design.

3. The method of claim 1 , wherein the control logic comprises one or more parts in a finite state machine and the first reconfigurable logic comprises one or more logic modules that can re-establish one or more state transition functions in the finite state machine.

4. The method of claim 1 , wherein the data path logic comprises a logic fan-in cone and the second reconfigurable logic comprises configuration bits representing original functionality of the logic fan-in cone.

5. The method of claim 1 , wherein the first and second reconfigurable logic are configured to be programmed at every power on by decrypting an encrypted bitstream.

6. The method of claim 1 , further comprising performing a logic synthesis on the reduced design and optimizing power-performance-area of the reduced design in accordance with the logic synthesis.

7. The method of claim 1 , wherein the CDFG representing the hardware IP design is generated from a register-transfer level or gate-level netlist of the hardware IP design.

8. The method of claim 1 , wherein the first and second reconfigurable logic comprises at least one of a hardware lookup table or a programmable interconnect.

9. An apparatus comprising one or more processors and at least one memory comprising computer executable instructions, the at least one memory and the computer executable instructions configured to, with the one or more processors, cause the apparatus to:
generate a control and data flow graph (CDFG) representing a hardware IP design, the CDFG comprising a plurality of control paths and/or data paths;
perform an entropy analysis of the CDFG to determine an entropy measure for each of the plurality of control paths and/or data paths, the entropy measure representing a complexity of an associated control path or an associated data path;
identify a subset of control paths and/or data paths for removal from the hardware IP design based at least in part on the entropy measure for each of the plurality of control paths and/or data paths;
generate a reduced design based at least in part on: (i) replacing control logic of the hardware IP design represented by each control path of the subset of control paths and/or data paths for removal with first reconfigurable logic, and (ii) replacing data path logic of the hardware IP design represented by each data path of the subset of control paths and/or data paths with second reconfigurable logic; and
provide access to the reduced design.

10. The apparatus of claim 9 , wherein access to the reduced design is provided in accordance with a determination that the reduced design is functionally correct with respect to the hardware IP design.

11. The apparatus of claim 9 , wherein the control logic comprises one or more parts in a finite state machine and the first reconfigurable logic comprises one or more logic modules that can re-establish one or more state transition functions in the finite state machine.

12. The apparatus of claim 9 , wherein the data path logic comprises a logic fan-in cone and the second reconfigurable logic comprises configuration bits representing original functionality of the logic fan-in cone.

13. The apparatus of claim 9 , wherein the first and second reconfigurable logic are configured to be programmed at every power on by decrypting an encrypted bitstream.

14. The apparatus of claim 9 , wherein the at least one memory and the computer executable instructions are further configured to, with the one or more processors, cause the apparatus to perform a logic synthesis on the reduced design and optimize power-performance-area of the reduced design in accordance with the logic synthesis.

15. The apparatus of claim 9 , wherein the CDFG representing the hardware IP design is generated from a register-transfer level or gate-level netlist of the hardware IP design.

16. The apparatus of claim 9 , wherein the first and second reconfigurable logic comprises at least one of a hardware lookup table or a programmable interconnect.

17. A computer program product comprising at least one non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising executable portions configured to cause one or more processors to:
generate a control and data flow graph (CDFG) representing a hardware IP design, the CDFG comprising a plurality of control paths and/or data paths;
perform an entropy analysis of the CDFG to determine an entropy measure for each of the plurality of control paths and/or data paths, the entropy measure representing a complexity of an associated control path or an associated data path;
identify a subset of control paths and/or data paths for removal from the hardware IP design based at least in part on the entropy measure for each of the plurality of control paths and/or data paths;
generate a reduced design based at least in part on: (i) replacing control logic of the hardware IP design represented by each control path of the subset of control paths and/or data paths for removal with first reconfigurable logic, and (ii) replacing data path logic of the hardware IP design represented by each data path of the subset of control paths and/or data paths with second reconfigurable logic; and
provide access to the reduced design.

18. The computer program product of claim 17 , wherein access to the reduced design is provided in accordance with a determination that the reduced design is functionally correct with respect to the hardware IP design.

19. The computer program product of claim 17 , wherein the control logic comprises one or more parts in a finite state machine and the first reconfigurable logic comprises one or more logic modules that can re-establish one or more state transition functions in the finite state machine.

20. The computer program product of claim 17 , wherein the data path logic comprises a logic fan-in cone and the second reconfigurable logic comprises configuration bits representing original functionality of the logic fan-in cone.

Assignees

• Univ Florida
• Intel Corp

Inventors

• Bhunia Swarup
• Alaql Abdulrahman
• Dorairaj Nij
• Kehlet David

Classifications

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F9/4498

  Finite state machines · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title