Oscillation detector and operating method thereof

Patent metadata

Field	Value
Publication number	US-12117472-B2
Application number	US-202217873795-A
Country	US
Kind code	B2
Filing date	Jul 26, 2022
Priority date	Jul 28, 2021
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

An oscillation detector includes an amplitude variation detection circuit configured to generate a first pulse signal by comparing levels of voltages with each other, a frequency variation detection circuit configured to generate a second pulse signal by filtering the first pulse signal and allowing to pass a frequency component that is less than or equal to a certain frequency among frequency components of the first pulse signal, and a time variation detection circuit configured to output an oscillation detection signal when the second pulse signal has consecutive pulses for a period of time.

First claim

What is claimed is:

1. An oscillation detector for detecting oscillation of a voltage, the oscillation detector comprising:
an amplitude variation detection circuit configured to generate a first pulse signal by comparing a level of a first voltage with a level of a second voltage;
a frequency variation detection circuit configured to generate a second pulse signal by filtering the first pulse signal and allowing a frequency component that is less than or equal to a reference frequency from among frequency components of the first pulse signal; and
a time variation detection circuit configured to output an oscillation detection signal based on the second pulse signal having consecutive pulses for a first time period.

2. The oscillation detector of claim 1 , wherein the amplitude variation detection circuit includes:
a low-pass filter configured to perform low-pass filtering on an external voltage to generate the first voltage;
a plurality of resistors configured to scale the external voltage to generate the second voltage; and
a comparator configured to generate the first pulse signal by comparing a level of the first voltage with the second voltage.

3. The oscillation detector of claim 1 , wherein the frequency variation detection circuit is further configured to:
generate the second pulse signal at a low level when a frequency of the first pulse signal is less than or equal to the reference frequency, and
generate the second pulse signal at a high level when the frequency of the first pulse signal exceeds the reference frequency.

4. The oscillation detector of claim 3 , wherein the frequency variation detection circuit is further configured to receive a reference clock signal, and
wherein a first frequency of the second pulse signal is equal to a second frequency of the reference clock signal.

5. The oscillation detector of claim 1 , wherein the frequency variation detection circuit includes a frequency counter configured to:
receive a reference clock signal, and
generate the second pulse signal at a high level when a number of cycles of the first pulse signal is greater than or equal to a reference value,
wherein the number of cycles of the first pulse signal being counted while the reference clock signal is at a high level.

6. The oscillation detector of claim 1 , wherein the time variation detection circuit is further configured to:
generate a plurality of frequency-divided signals having different frequencies by dividing a frequency of the second pulse signal, and
output the oscillation detection signal based on the plurality of frequency-divided signals.

7. The oscillation detector of claim 6 , wherein the time variation detection circuit includes:
a time counter configured to divide the frequency of the second pulse signal;
an AND gate configured to perform an AND operation on the plurality of frequency-divided signals; and
a memory circuit configured to generate the oscillation detection signal indicating occurrence of oscillation by maintaining a pulse of a signal generated based on the AND operation at a high level.

8. An oscillation detector for detecting oscillation of a voltage, the oscillation detector comprising:
an amplitude variation detection circuit configured to generate a first pulse signal by comparing a level of a first voltage with a level of a second voltage;
a frequency variation detection circuit configured to count a number of pulses of the first pulse signal in a first time period and generate a second pulse signal based on the number of pulses; and
a time variation detection circuit configured to generate a plurality of frequency-divided signals having different frequencies by dividing a frequency of the second pulse signal and output an oscillation detection signal based on the plurality of frequency-divided signals.

9. The oscillation detector of claim 8 , wherein the first voltage is obtained by scaling an external voltage input, and the second voltage corresponds to a direct current (DC) component of the external voltage input, and
wherein the amplitude variation detection circuit is further configured to output the first pulse signal by generating a pulse signal when the first voltage is greater than the second voltage.

10. The oscillation detector of claim 8 , wherein the frequency variation detection circuit is further configured to receive a reference clock signal,
generate the second pulse signal at a low level when the number of pulses of the first pulse signal is less than a reference value while the reference clock signal is at a high level, and
generate the second pulse signal at a high level starting from a moment when the number of pulses is at least the reference value while the reference clock signal is at the high level.

11. The oscillation detector of claim 10 , wherein the frequency of the second pulse signal is equal to a frequency of the reference clock signal.

12. The oscillation detector of claim 10 , wherein a first pulse width of the second pulse signal is less than or equal to a second pulse width of the reference clock signal.

13. The oscillation detector of claim 8 , wherein the time variation detection circuit is further configured to generate an output signal by performing an AND operation on the plurality of frequency-divided signals and generate the oscillation detection signal indicating occurrence of oscillation when the output signal is maintained at a low level for a reference time period.

14. The oscillation detector of claim 13 , wherein the time variation detection circuit is further configured to generate the oscillation detection signal at a high level starting from a moment when a pulse of the output signal occurs after a lapse of the reference time period during which the output signal is at the low level.

15. The oscillation detector of claim 8 , wherein the amplitude variation detection circuit includes:
a comparator;
a low-pass filter between a first node and a first input terminal of the comparator, an external voltage being applied to the first node;
a first resistor connected between the first node and a second node connected to a second input terminal of the comparator; and
a second resistor connected between the second node and ground.

16. The oscillation detector of claim 10 , wherein the time variation detection circuit is further configured to generate the plurality of frequency-divided signals by determining a plurality of division factors based on a frequency of the reference clock signal.

17. An oscillation detector comprising:
a receiver configured to receive an external voltage; and
a processor configured to:
generate a first voltage by performing low-pass filtering on the external voltage;
generate a second voltage by scaling the external voltage;
generate a first signal by comparing the first voltage with the second voltage;
generate a second signal by filtering the first signal to pass a frequency component that satisfies a first criteria; and
output an oscillation detection signal based on the second signal satisfying a second criteria.

18. The oscillation detector of claim 17 , wherein the second signal satisfies the second criteria when the second signal has consecutive pulses for a first time period.

19. The oscillation detector of claim 17 , wherein the processor is further configured to generate the second signal when a number of cycles of the first signal is greater than or equal to a reference value.

20. The oscillation detector of claim 17 , wherein the processor is

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaeseung
• Yoo Sungmin
• Kong Taehwang
• Yang Junhyeok

Classifications

• G01R29/027 Primary

  Indicating that a pulse characteristic is either above or below a predetermined value or within or beyond a predetermined range of values · CPC title

• G01R19/0038

  Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller (comparing pulses or pulse trains according to amplitude) · CPC title

• G01R23/15

  Indicating that frequency of pulses is either above or below a predetermined value or within or outside a predetermined range of values, by making use of non-linear or digital elements {(indicating that pulse width is above or below a certain limit)} · CPC title

• G01R23/10 Primary

  by converting frequency into a train of pulses, which are then counted {, i.e. converting the signal into a square wave} · CPC title

• G01R23/165 Primary

  using filters · CPC title