Semiconductor device and display unit
US-2018175246-A1 · Jun 21, 2018 · US
Method for manufacturing display device, and display device
US12114540B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12114540-B2 |
| Application number | US-201817270446-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 24, 2018 |
| Priority date | Aug 24, 2018 |
| Publication date | Oct 8, 2024 |
| Grant date | Oct 8, 2024 |
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- Title
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Abstract
Official abstract text for this publication.
A display device (1) includes: a substrate (2); and a first transistor (1a) formed on the substrate (2). The first transistor (1a) includes: an oxide semiconductor layer (4) formed on the substrate (2); a gate insulating layer (5) formed on the oxide semiconductor layer (4); and a gate electrode (6) formed on the gate insulating layer (5). The oxide semiconductor layer (4) includes: a conductive region (4a) provided with conductivity; a first resistance region (4b) positioned below the gate electrode (6); and a second resistance region (4c) provided between the conductive region (4a) and the first resistance region (4b), and positioned outside the gate electrode (6). The first resistance (4b) is larger in resistance than the second resistance region (4c).
First claim
Opening claim text (preview).
The invention claimed is: 1. A display device comprising: a substrate; a first transistor formed on the substrate; and a second transistor formed on the substrate, the first transistor including: a first oxide semiconductor layer formed on the substrate; a first gate insulating layer formed on the first oxide semiconductor layer; and a first gate electrode formed on the first gate insulating layer, the first oxide semiconductor layer including: a first conductive region provided with conductivity; a first central resistance region positioned below the first gate electrode; and a first lateral resistance region provided between the first conductive region and the first central resistance region, and positioned outside the first gate electrode, and the first central resistance region being larger in resistance than the first lateral resistance region, and the first gate insulating layer of the first transistor covering only the first central resistance region and the first lateral resistance region of the first oxide semiconductor layer, wherein the second transistor includes: a second oxide semiconductor layer formed on the substrate; a second gate insulating layer formed on the second oxide semiconductor layer; and a second gate electrode formed on the second gate insulating layer, the second oxide semiconductor layer includes: a second conductive region provided with conductivity; and a second central resistance region positioned below the second gate electrode, the second gate insulating layer matches the second central resistance region and the second gate electrode in shape, and the second central resistance region is provided in contact with the second conductive region. 2. The display device according to claim 1 , wherein the first gate insulating layer is longer in a channel length direction than the first gate electrode. 3. The display device according to claim 1 , wherein the first gate insulating layer matches the first central resistance region and the first gate electrode in shape.
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Classifications
characterised by the gate electrodes · CPC title
- H10D30/6755Primary
Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title
of thin-film transistors [TFT] · CPC title
characterised by the doping profiles, e.g. having lightly-doped source or drain extensions · CPC title
Subject matter not provided for in other groups of this subclass · CPC title
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Frequently asked questions
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- What does patent US12114540B2 cover?
- A display device (1) includes: a substrate (2); and a first transistor (1a) formed on the substrate (2). The first transistor (1a) includes: an oxide semiconductor layer (4) formed on the substrate (2); a gate insulating layer (5) formed on the oxide semiconductor layer (4); and a gate electrode (6) formed on the gate insulating layer (5). The oxide semiconductor layer (4) includes: a conductiv…
- Who is the assignee on this patent?
- Sharp Kk
- What technology area does this patent fall under?
- Primary CPC classification H10D30/6755. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 08 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).