Three-dimensional memory arrays with layer selector transistors

Patent metadata

Field	Value
Publication number	US-12114479-B2
Application number	US-202117368329-A
Country	US
Kind code	B2
Filing date	Jul 6, 2021
Priority date	Nov 20, 2019
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

First claim

The invention claimed is:

1. An integrated circuit (IC) device, comprising:
an arrangement that includes two or more memory cells, a transistor, and a bitline; and
an interconnect structure,
wherein:
an individual memory cell of the arrangement includes an access transistor,
each of the transistor and the access transistor includes a first region and a second region, wherein one of the first region and the second region is a source region and another one of the first region and the second region is a drain region,
the first regions of the access transistors of the two or more memory cells of the arrangement are directly electrically connected to one another and to the bitline, and the bitline is directly electrically connected to the first region of the transistor, and
the second region of the transistor is directly electrically connected to the interconnect structure.

2. The IC device according to claim 1 , wherein:
the arrangement further includes a local interconnect structure, and
a gate electrode of the transistor is coupled to the local interconnect structure.

3. The IC device according to claim 2 , wherein:
the arrangement further includes two or more further memory cells, a further transistor, and a further bitline,
each memory cell of the two or more further memory cells of the arrangement includes an access transistor,
a first region of the access transistor of each of the two or more further memory cells of the arrangement is coupled to the further bitline,
the further bitline is coupled to a first region of the further transistor,
the first region of the access transistor of each of the two or more further memory cells of the arrangement and the first region of the further transistor is either a source region or a drain region, and
a gate electrode of the further transistor is coupled to the local interconnect structure.

4. The IC device according to claim 3 , wherein:
the interconnect structure is a first interconnect structure,
the IC device further includes a second interconnect structure,
a second region of the further transistor is coupled to the second interconnect structure, and
the second region of the further transistor is another one of the source region or the drain region than the first region of the transistor.

5. The IC device according to claim 3 , wherein at least one of the transistor and the further transistor is a thin film transistor (TFT).

6. The IC device according to claim 1 , wherein the interconnect structure is substantially perpendicular to a support structure over which the arrangement is provided.

7. The IC device according to claim 1 , wherein:
the arrangement is a first arrangement, the transistor is a first transistor, and the bitline is a first bitline,
the IC device further includes a second arrangement that includes two or more memory cells, a second transistor, and a second bitline,
each of the two or more memory cells of the second arrangement is coupled to the second bitline, and
the second transistor is coupled to the interconnect structure.

8. The IC device according to claim 7 , wherein:
an individual memory cell of the second arrangement includes an access transistor, and
each of the two or more memory cells of the second arrangement is coupled to the second bitline by having a first region of the access transistor of each of the two or more memory cells of the second arrangement being coupled to the second bitline, wherein the first region of the access transistor of each of the two or more memory cells of the second arrangement is either a source region or a drain region.

9. The IC device according to claim 8 , wherein the second bitline is coupled to a first region of the second transistor, wherein the first region of the second transistor is either a source region or a drain region.

10. The IC device according to claim 9 , wherein a second region of the second transistor is coupled to the interconnect structure, wherein the second region of the second transistor is another one of the source region or the drain region of the second transistor than the first region of the second transistor.

11. The IC device according to claim 10 , wherein:
the first arrangement further includes a first local interconnect structure, and
a gate electrode of the first transistor is coupled to the first local interconnect structure.

12. The IC device according to claim 11 , wherein:
the first arrangement further includes two or more further memory cells, a further first transistor, and a further first bitline,
each memory cell of the two or more further memory cells of the first arrangement includes an access transistor,
a first region of the access transistor of each of the two or more further memory cells of the first arrangement is coupled to the further first bitline,
the first region of the access transistor of each of the two or more further memory cells of the first arrangement is either a source region or a drain region of the access transistor of each of the two or more further memory cells of the first arrangement,
the further first bitline is coupled to a first region of the further first transistor,
the first region of the further first transistor is either a source region or a drain region of the access transistor of the further first transistor, and
a gate electrode of the further first transistor is coupled to the first local interconnect structure.

13. The IC device according to claim 12 , wherein:
the interconnect structure is a first interconnect structure,
the IC device further includes a second interconnect structure,
a second region of the further first transistor is coupled to the second interconnect structure, and
the second region of the further first transistor is another one of the source region or the drain region of the access transistor of the further first transistor than the first region of the further first transistor.

14. The IC device according to claim 13 , wherein:
the second arrangement further includes two or more further memory cells, a further second transistor, and a further second bitline,
each memory cell of the two or more further memory cells of the second arrangement includes an access transistor,
a first region of the access transistor of each of the two or more further memory cells of the second arrangement is coupled to the further second bitline, and the further second bitline is coupled to a first region of the further second transistor,
a second region of the further second transistor is coupled to the second interconnect structure,
the first region of the access transistor of each of the two or more further memory cells of the second arrangement is either a source region or a drain region of the access transistor of each of the two or more further memory cells of the second arrangement,
the first region of the further second transistor is either a source region or a drain region of the further second transistor, and
the second region of the further second transistor is another one of the source region or the drain region of the further second transistor.

15. The IC device according to claim 13 , wherein at least one of the first interconnect structure and the second interconnect structure is substantially perpendicular to a support structure over which the first and the second arrangements are provided.

16. The IC device according to claim 1 , wherein the two or more memory cells include a first memory cell and a second memory cell, the second region of the access transistor of the first memory cell is electrically connected to a capacitor

Assignees

• Intel Corp

Inventors

• Gomes Wilfred
• Kobrinsky Mauro J
• Sharma Abhishek A
• Kumar Rajesh
• Phoa Kinyip
• Tan Elliot
• Ghani Tahir
• Sivakumar Swaminathan

Classifications

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10D30/674

  characterised by the active materials · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title