Delta-sigma modulator

Patent metadata

Field	Value
Publication number	US-12113552-B2
Application number	US-202218066276-A
Country	US
Kind code	B2
Filing date	Dec 14, 2022
Priority date	Dec 24, 2021
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

Provided is a delta-sigma modulator including a first integral unit configured to integrate an input analog signal, a second integral unit configured to integrate a signal output by the first integral unit, a quantizer configured to quantize a signal output by the second integral unit, a DA converter configured to perform DA conversion on an output of the quantizer and output a feedback signal to be fed back to the first integral unit, and a control unit configured to perform control to cause the first integral unit and the second integral unit to perform different integral operations during a first period and a second period, in which the second integral unit is configured to receive the feedback signal output by the DA converter via the first integral unit and integrate the feedback signal during the first period and the second period.

First claim

What is claimed is:

1. A delta-sigma modulator comprising:
a first integral unit configured to integrate an input analog signal;
a second integral unit configured to integrate a signal output by the first integral unit;
a quantizer configured to quantize a signal output by the second integral unit;
a digital-to-analog (DA) converter configured to perform DA conversion on an output of the quantizer and output a feedback signal to be fed back to the first integral unit; and
a control unit configured to perform control to cause the first integral unit and the second integral unit to perform different integral operations during a first period and a second period, wherein
the second integral unit is configured to receive the feedback signal output by the DA converter via the first integral unit and integrate the feedback signal during the first period and the second period, and
the control unit is configured to control the second integral unit to be caused to operate as an integrator in which a feedback coefficient during the second period is higher than a feedback coefficient during the first period.

2. The delta-sigma modulator according to claim 1 , wherein
the control unit is configured to control the first integral unit to be caused to operate as an integrator in which a feedback coefficient during the second period is lower than a feedback coefficient during the first period.

3. The delta-sigma modulator according to claim 2 , wherein
the control unit is configured to control the first integral unit to be caused to operate as an integrator with a feedback coefficient of 1 during the first period and control the first integral unit to be caused to operate as an integrator with a feedback coefficient of 0 during the second period, and to control the second integral unit to be caused to operate as an integrator with a feedback coefficient of 1 during the first period and control the second integral unit to be caused to operate as an integrator with a feedback coefficient greater than 1 during the second period.

4. The delta-sigma modulator according to claim 2 , wherein
the first integral unit is configured to output, to the second integral unit, the feedback signal output by the DA converter at a same gain as a gain at a time when the feedback signal is input to the first integral unit during the second period.

5. The delta-sigma modulator according to claim 2 , wherein
the first integral unit includes
an addition unit to which the feedback signal is input,
a first switching unit configured to output a signal, which is to be output by the addition unit, at a gain of 1 during the first period, and to output the signal at a gain of 1 and a gain of 0 alternately during the second period, and
a feedback path for returning an output of the first switching unit to an input of the addition unit, wherein
the first integral unit is configured to output a signal via the feedback path during both the first period and the second period.

6. The delta-sigma modulator according to claim 2 , wherein
the second integral unit includes a second switching unit configured to output a signal from the first integral unit with delay during the first period and to output the signal from the first integral unit without delay during the second period.

7. The delta-sigma modulator according to claim 1 , wherein
the control unit is configured to control the first integral unit to be caused to operate as an integrator with a feedback coefficient of 1 during the first period and control the first integral unit to be caused to operate as an integrator with a feedback coefficient of 0 during the second period, and to control the second integral unit to be caused to operate as an integrator with a feedback coefficient of 1 during the first period and control the second integral unit to be caused to operate as an integrator with a feedback coefficient greater than 1 during the second period.

8. The delta-sigma modulator according to claim 7 , wherein
the first integral unit is configured to output, to the second integral unit, the feedback signal output by the DA converter at a same gain as a gain at a time when the feedback signal is input to the first integral unit during the second period.

9. The delta-sigma modulator according to claim 7 , wherein
the first integral unit includes
an addition unit to which the feedback signal is input,
a first switching unit configured to output a signal, which is to be output by the addition unit, at a gain of 1 during the first period, and to output the signal at a gain of 1 and a gain of 0 alternately during the second period, and
a feedback path for returning an output of the first switching unit to an input of the addition unit, wherein
the first integral unit is configured to output a signal via the feedback path during both the first period and the second period.

10. The delta-sigma modulator according to claim 7 , wherein
the second integral unit includes a second switching unit configured to output a signal from the first integral unit with delay during the first period and to output the signal from the first integral unit without delay during the second period.

11. The delta-sigma modulator according to claim 1 , wherein
the first integral unit is configured to output, to the second integral unit, the feedback signal output by the DA converter at a same gain as a gain at a time when the feedback signal is input to the first integral unit during the second period.

12. The delta-sigma modulator according to claim 11 , wherein
the first integral unit includes
an addition unit to which the feedback signal is input,
a first switching unit configured to output a signal, which is to be output by the addition unit, at a gain of 1 during the first period, and to output the signal at a gain of 1 and a gain of 0 alternately during the second period, and
a feedback path for returning an output of the first switching unit to an input of the addition unit, wherein
the first integral unit is configured to output a signal via the feedback path during both the first period and the second period.

13. The delta-sigma modulator according to claim 11 , wherein
the second integral unit includes a second switching unit configured to output a signal from the first integral unit with delay during the first period and to output the signal from the first integral unit without delay during the second period.

14. The delta-sigma modulator according to claim 1 , wherein
the first integral unit includes
an addition unit to which the feedback signal is input,
a first switching unit configured to output a signal, which is to be output by the addition unit, at a gain of 1 during the first period, and to output the signal at a gain of 1 and a gain of 0 alternately during the second period, and
a feedback path for returning an output of the first switching unit to an input of the addition unit, wherein
the first integral unit is configured to output a signal via the feedback path during both the first period and the second period.

15. The delta-sigma modulator according to claim 14 , wherein
the first switching unit includes a first delay element configured to delay a signal output by the addition unit, an amplifier configured to output a signal, which is output by the addition unit, at a gain of 0, and a multiplexer to which an output of the first delay element and an output of the amplifier are input.

16. The delta-sigma modulator according to claim 15 , wherein
the delta-sigma modulator is an incremental analog-to-digital (AD) converter configured to perform

Assignees

• Asahi Kasei Microdevices Corp

Inventors

• Ohara Kazuma

Classifications

• H03M3/02

  Delta modulation, i.e. one-bit differential modulation {(H03M3/30 takes precedence)} · CPC title

• H03M3/43

  the quantiser being a single bit one · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/438

  the modulator having a higher order loop filter in the feedforward path · CPC title

• H03M3/394

  among different orders of the loop filter · CPC title