Single-ended to differential-ended converter circuit, successive-approximation register analog-to-digital converter utilizing same, and method of converting single-ended signal to differential-ended signal

Patent metadata

Field	Value
Publication number	US-12113544-B2
Application number	US-202217864464-A
Country	US
Kind code	B2
Filing date	Jul 14, 2022
Priority date	Nov 3, 2021
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A method of converting a single-ended signal to a differential-ended signal includes the following steps: providing a first sampling capacitor having a first end and a second end; providing a second sampling capacitor having a third end and a fourth end; at a first time point, controlling the first end to receive a single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of the swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and at a second time point, controlling the second end and the fourth end to receive the reference voltage. The first end and the third end output a differential signal after the second time point which is later than the first time point.

First claim

What is claimed is:

1. A single-ended to differential-ended converter circuit for receiving a single-ended signal and outputting a differential signal at a first output node and a second output node, comprising:
a first sampling capacitor having a first end and a second end, the first end being coupled to the first output node, and the second end receiving a reference voltage;
a second sampling capacitor having a third end and a fourth end, the third end being coupled to the second output node;
a switch group coupled to the first output node, the second output node, and the fourth end; and
a logic circuit coupled to the switch group and configured to control the switch group according to a clock;
wherein at a first time point, the switch group couples the first output node and the first end to the single-ended signal, couples the second output node and the third end to the reference voltage or a middle voltage value of a swing of the single-ended signal, and couples the fourth end to the single-ended signal;
wherein at a second time point, the switch group couples the fourth end to the reference voltage; and
wherein the differential signal is outputted after the second time point which is later than the first time point;
wherein the first time point corresponds to one of a rising edge and a falling edge of the clock, and the second time point corresponds to another of the rising edge and the falling edge of the clock.

2. The single-ended to differential-ended converter circuit of claim 1 , wherein the switch group comprises:
a first switch coupled to the first output node and the first end;
a second switch coupled to the second output node and the third end; and
a third switch coupled to the fourth end;
wherein at the first time point, the first switch is turned on to couple the first output node and the first end to the single-ended signal, the second switch is turned on to couple the second output node and the third end to the reference voltage or the middle voltage value of the swing of the single-ended signal, and the third switch couples the fourth end to the single-ended signal; and
wherein at the second time point, the first switch and the second switch are turned off, and the third switch couples the fourth end to the reference voltage.

3. The single-ended to differential-ended converter circuit of claim 1 further comprising:
a first capacitor having a fifth end and a sixth end, the fifth end being coupled to the first output node, and the sixth end receiving the reference voltage; and
a second capacitor having a seventh end and an eighth end, the seventh end being coupled to the second output node, and the eighth end receiving the reference voltage.

4. The single-ended to differential-ended converter circuit of claim 1 further comprising:
a first capacitor group comprising a plurality of first capacitors, an end of the first capacitors being coupled to the first output node, and another end of the first capacitors being coupled to the reference voltage; and
a second capacitor group comprising a plurality of second capacitors, an end of the second capacitors being coupled to the second output node, and another end of the second capacitors being coupled to the reference voltage.

5. The single-ended to differential-ended converter circuit of claim 4 , wherein capacitance values of the first capacitors increase in a binary progression, and capacitance values of the second capacitors increase in a binary progression.

6. A successive-approximation register (SAR) analog-to-digital converter (ADC), comprising:
a comparator having a first input terminal and a second input terminal and configured to generate a comparison result;
a SAR coupled to the comparator and configured to store the comparison result;
a first sampling capacitor having a first end and a second end, the first end being coupled to the first input terminal, and the second end receiving a reference voltage;
a second sampling capacitor having a third end and a fourth end, the third end being coupled to the second input terminal;
a first capacitor group comprising a plurality of first capacitors, an end of the first capacitors being coupled to the first input terminal;
a first switch group coupled to another end of the first capacitors;
a second capacitor group comprising a plurality of second capacitors, an end of the second capacitors being coupled to the second input terminal;
a second switch group coupled to another end of the second capacitors;
a control circuit coupled to the SAR and configured to control the first switch group and the second switch group according to the comparison result; and
a third switch group coupled to the first input terminal, the second input terminal, and the fourth end;
wherein at a first time point, the third switch group couples the first input terminal and the first end to a single-ended signal, couples the second input terminal and the third end to the reference voltage or a middle voltage value of a swing of the single-ended signal, and couples the fourth end to the single-ended signal;
wherein the third switch group couples the fourth end to the reference voltage at a second time point which is later than the first time point.

7. The SAR ADC of claim 6 , wherein the third switch group comprises:
a first switch coupled to the first input terminal and the first end;
a second switch coupled to the second input terminal and the third end; and
a third switch coupled to the fourth end;
wherein at the first time point, the first switch is turned on to couple the first input terminal and the first end to the single-ended signal, the second switch is turned on to couple the second input terminal and the third end to the reference voltage or the middle voltage value of the swing of the single-ended signal, and the third switch couples the fourth end to the single-ended signal; and
wherein at the second time point, the first switch and the second switch are turned off, and the third switch couples the fourth end to the reference voltage.

8. The SAR ADC of claim 6 , wherein capacitance values of the first capacitors increase in a binary progression, and capacitance values of the second capacitors increase in a binary progression.

9. The SAR ADC of claim 6 further comprising:
a logic circuit coupled to the third switch group and configured to control the third switch group according to a clock;
wherein the first time point corresponds to one of a rising edge and a falling edge of the clock, and the second time point corresponds to another of the rising edge and the falling edge of the clock.

10. A method of converting a single-ended signal to a differential signal, comprising:
providing a first sampling capacitor which has a first end and a second end;
providing a second sampling capacitor which has a third end and a fourth end;
at a first time point, controlling the first end to receive the single-ended signal, controlling the second end to receive a reference voltage, controlling the third end to receive the reference voltage or a middle voltage value of a swing of the single-ended signal, and controlling the fourth end to receive the single-ended signal; and
at a second time point, controlling the second end to receive the reference voltage and controlling the fourth end to receive the reference voltage;
wherein the first end and the third end output the differential signal after the second time point which is later than the first time point;
wherein the first time point corresponds to one of a rising edge and a falling edge of a clock, and the second time point corresponds to another of the rising edge and the falling edge of the clock.

11. The

Assignees

• Realtek Semiconductor Corp

Inventors

• Shih Sheng-Yen
• Huang Shih-Hsiung
• Hong Wei-Cian

Classifications

• H03M3/04

  Differential modulation with several bits {, e.g. differential pulse code modulation [DPCM] (H03M3/30 takes precedence)} · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/38 Primary

  sequentially only, e.g. successive approximation type (converting more than one bit per step H03M1/14) · CPC title

• H03M1/0682 Primary

  using a differential network structure, i.e. symmetrical with respect to ground · CPC title