Semiconductor device

US12113009B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12113009-B2
Application numberUS-202318454582-A
CountryUS
Kind codeB2
Filing dateAug 23, 2023
Priority dateSep 19, 2018
Publication dateOct 8, 2024
Grant dateOct 8, 2024

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other in a thickness direction, with the semiconductor element mounted on the mounting-portion front surface. The sealing resin includes a resin front surface, a resin back surface and a resin side surface connecting the resin front surface and the resin back surface. The mounting-portion back surface of the first lead is flush with the resin back surface. The first terminal portion includes a first-terminal-portion back surface exposed from the resin back surface, in a manner such that the first-terminal-portion back surface extends to the resin side surface.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor device comprising: a metal-oxide semiconductor field-effect transistor (MOSFET) semiconductor element provided with a first electrode, a second electrode, and a third electrode; a first lead that includes a mounting portion on which the MOSFET semiconductor element is mounted, the mounting portion includes a mounting-portion front surface and a mounting-portion back surface that are opposite to each other in a thickness direction, the MOSFET semiconductor element being mounted on the mounting-portion front surface; a second lead disposed on one side of the first lead as viewed in plan with respect to the mounting-portion front surface, the second lead comprising three terminal portions that extend away from the first lead to an external edge of the semiconductor device; a third lead disposed on the one side of the first lead, and under a condition the one side of the first lead is above the second lead and the third lead as viewed in plan, the second lead is disposed on a right side of the third lead; a sealing resin that covers the MOSFET semiconductor element and respective portions of the first lead, the second lead and the third lead, the sealing resin includes a resin front surface, a resin back surface and a resin side surface, the resin front surface and the resin back surface being opposite to each other in a thickness direction, the resin side surface connects the resin front surface and the resin back surface, and a plurality of bonding wires, wherein the mounting-portion back surface is flush with the resin back surface, and includes a portion that is exposed from the sealing resin, bottom surfaces of the three terminal portions of the second lead are substantially flush with at least the portion of the mounting-portion back surface that is exposed from the sealing resin, and at least portions of the bottom surfaces and end surfaces of the three terminal portions are exposed from the sealing resin, a bottom surface of the third lead is substantially flush with at least the portion of the mounting-portion back surface that is exposed from the sealing resin, and at least the bottom surface and an end surface of the third lead is also exposed from the sealing resin, the plurality of bonding wires electrically connect the second electrode of the MOSFET semiconductor element to the second lead, wherein the sealing resin covers all of each of the plurality of bonding wires, and the plurality of bonding wires extend in a common direction perpendicular to the thickness direction. 2. The semiconductor device according to claim 1 , wherein the first electrode of the MOSFET semiconductor element is electrically connected to the first lead. 3. The semiconductor device according to claim 1 , further comprising another bonding wire that electrically connects the third electrode of the MOSFET semiconductor element to the third lead, wherein the sealing resin covers all of the another bonding wire. 4. The semiconductor device according to claim 1 , wherein the semiconductor device is rectangular as viewed in plan. 5. The semiconductor device according to claim 4 , wherein at least one side of the semiconductor device as viewed in plan is substantially 10 mm in length. 6. The semiconductor device according to claim 1 , wherein a thickness of each of the second lead and the third lead is in an inclusive range of 0.08 mm to 0.5 mm. 7. The semiconductor device according to claim 1 , wherein each of the first lead, the second lead, and the third lead comprises a metal. 8. The semiconductor device according to claim 1 , wherein, as viewed in plan, a footprint of the first lead includes a center of the semiconductor device, and the first lead extends away from the second lead and the third lead to an upper edge of the semiconductor device. 9. The semiconductor device according to claim 1 , wherein, as viewed in plan, an edge of the first lead includes at least one first-lead terminal, and a first-lead terminal portion. 10. The semiconductor device according to claim 9 , wherein the first-lead terminal portion, as viewed in plan, is rectangular. 11. The semiconductor device according to claim 9 , wherein a front surface of the first-lead terminal portion is flush with the mounting-portion front surface. 12. The semiconductor device according to claim 9 , wherein a back surface of the first-lead terminal portion is flush with the mounting-portion back surface. 13. The semiconductor device according to claim 9 , wherein the first-lead terminal portion connects a first lead terminal front surface with a first lead terminal back surface and includes a front-lead terminal end surface that is exposed from the sealing resin. 14. The semiconductor device according to claim 1 , wherein the third lead, as viewed in plan, is rectangular. 15. The semiconductor device according to claim 1 , wherein each of the terminal portions of the second lead are separated by a common predetermined pitch. 16. The semiconductor device according to claim 1 , wherein one edge of the first lead includes at least two projections that extend, as viewed in plan, from a main external edge of the first lead. 17. The semiconductor device according to claim 1 , further comprising a fourth lead, wherein at least a portion of the fourth lead is rectangular in shape.

Assignees

Inventors

Classifications

  • Package configurations · CPC title

  • by a substrate and the encapsulations · CPC title

  • Bond wires · CPC title

  • characterised by arrangements for sealing or adhesion · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

Patent family

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External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12113009B2 cover?
A semiconductor device includes a semiconductor element, a first lead including a mounting portion for the semiconductor element and a first terminal portion connected to the mounting portion, and a sealing resin covering the semiconductor element and a portion of the first lead. The mounting portion has a mounting-portion front surface and a mounting-portion back surface opposite to each other…
Who is the assignee on this patent?
Rohm Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W70/658. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 08 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).