Package having an electronic component and an encapsulant encapsulating a dielectric layer and a semiconductor die of the electronic component

Patent metadata

Field	Value
Publication number	US-12112992-B2
Application number	US-202318107800-A
Country	US
Kind code	B2
Filing date	Feb 9, 2023
Priority date	Apr 22, 2020
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A package includes: an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and an encapsulant encapsulating the dielectric layer and the semiconductor die. The encapsulant is a mold compound having different material properties than the dielectric layer. A method of manufacturing package is also described.

First claim

What is claimed is:

1. A package, comprising:
an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and
an encapsulant encapsulating the dielectric layer and the semiconductor die,
wherein the encapsulant is a mold compound having different material properties than the dielectric layer, and
wherein the electronic component further includes an adhesive layer that further promotes adhesion between the dielectric layer and the semiconductor die.

2. The package of claim 1 , wherein the active area has at least one transistor and/or at least one diode.

3. The package of claim 1 , wherein the active area has a thickness of less than 1 μm.

4. The package of claim 1 , wherein the semiconductor die has unprocessed semiconductor material with a thickness of less than 150 μm.

5. The package of claim 1 , wherein the semiconductor die has a thickness in a range from 1 μm to 200 μm.

6. The package of claim 1 , wherein the semiconductor die has a first portion that comprises a semiconductor material having an electric resistivity of at least 500 Ωcm and a second portion that comprises a semiconductor material having an electric resistivity of less than 100 Ωcm.

7. The package of claim 6 , wherein the dielectric layer adjoins the first portion of the semiconductor die.

8. The package of claim 1 , wherein the semiconductor die is a silicon-on-insulator die.

9. The package of claim 1 , wherein the semiconductor die includes at least one material selected from the group consisting of silicon, germanium, gallium nitride, gallium arsenide, indium phosphide, silicon carbide, sapphire, diamond, and diamond-like coating.

10. The package of claim 1 , wherein the dielectric layer is made of a temperature curable material.

11. The package of claim 1 , further comprising an electrically conductive back end of line structure on a main surface of the semiconductor die opposing another main surface of the semiconductor die on the dielectric layer.

12. The package of claim 11 , wherein the back end of line structure is directly connected to the active area of the semiconductor die.

13. The package of claim 11 , further comprising at least one electrically conductive protrusion protruding beyond the back end of line structure.

14. The package of claim 1 , further comprising a carrier at least partially encapsulated by the encapsulant and electrically connected with the electronic component.

15. The package of claim 14 , wherein the encapsulant encapsulates both the electronic component and the carrier.

16. The package of claim 1 , wherein the dielectric layer is a double mold layer composed of a mold plate and a mold foil.

17. The package of claim 1 , wherein the dielectric layer comprises a resin matrix and filler particles embedded in the resin matrix.

18. The package of claim 1 , wherein the dielectric layer comprises a polymer.

19. A method of manufacturing a package, the method comprising:
providing an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and
encapsulating the dielectric layer and the semiconductor die by an encapsulant,
wherein the encapsulant is a mold compound having different material properties than the dielectric layer, and
wherein the electronic component further includes an adhesive layer that further promotes adhesion between the dielectric layer and the semiconductor die.

20. A package, comprising:
an electronic component that includes a dielectric layer as a base and a semiconductor die attached on top of the dielectric layer, the semiconductor die having an active area with monolithically integrated circuit elements; and
an encapsulant encapsulating the dielectric layer and the semiconductor die,
wherein the encapsulant is a mold compound having different material properties than the dielectric layer, and
wherein the dielectric layer comprises a polymer.

Assignees

• Infineon Technologies Ag

Inventors

• Porwol Daniel
• Fischer Thomas
• Seidel Uwe
• Steltenpohl Anton

Classifications

• H10W70/09

  extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10P72/7434

  used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate · CPC title

• H10P72/7416

  used during dicing or grinding · CPC title

• H10P72/7402

  Wafer tapes, e.g. grinding or dicing support tapes · CPC title