Ceramic electronic device and manufacturing method of the same

US12112893B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12112893-B2
Application numberUS-202217860946-A
CountryUS
Kind codeB2
Filing dateJul 8, 2022
Priority dateJul 28, 2021
Publication dateOct 8, 2024
Grant dateOct 8, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being Ni, the internal electrode layers being alternately exposed to two end faces of the multilayer chip opposite to each other, and external electrodes, each of which is provided on each of the two end faces. Each of the external electrodes includes a base layer contacting the internal electrode layers, a main component of the base layer being Cu. The base layer includes Ni of 1 wt % or more and 10 wt % or less on a presumption that an amount of Cu is 100 wt %.

First claim

Opening claim text (preview).

What is claimed is: 1. A ceramic electronic component device: a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being Ni, the internal electrode layers being alternately exposed to two end faces of the multilayer chip opposite to each other; and external electrodes, each of which is provided on each of the two end faces, wherein each of the external electrodes includes a base layer contacting the internal electrode layers, a main component of the base layer being Cu, and wherein the base layer includes Ni of 1 wt % or more and 5.0 wt % or less on a presumption that an amount of Cu is 100 wt %. 2. The ceramic electronic device as claimed in claim 1 , wherein the base layer includes an oxide including Ni and Zn. 3. The ceramic electronic device as claimed in claim 1 , wherein an average grain diameter of the oxide including Ni and Zn is 1 μm or less, in the base layer. 4. The ceramic electronic device as claimed in claim 1 , wherein the base layer includes a glass component of 7 weight parts or more and 13 weight parts or less with respect to Cu. 5. The ceramic electronic device as claimed in claim 1 , wherein the base layer includes Ni of 3 wt % or more on a presumption that the amount of Cu is 100 wt %. 6. The ceramic electronic device as claimed in claim 1 , wherein the base layer includes Ni of 5 wt % or more on a presumption that the amount of Cu is 100 wt %. 7. The ceramic electronic device as claimed in claim 1 , wherein the base layer includes Ni of 7 wt % or less on a presumption that the amount of Cu is 100 wt %. 8. A manufacturing method of a ceramic electronic device comprising: preparing a ceramic multilayer structure having a substantially rectangular parallelepiped shape in which dielectric green sheets including a main component ceramic and metal conductive pastes for internal electrode layers including Ni as a main component metal are alternately stacked, the metal conductive pastes being alternately exposed to two end faces of the ceramic multilayer structure opposite to each other; forming a multilayer chip by firing the ceramic multilayer structure; providing metal conductive pastes for base layers contacting the two end faces, a main component metal of the metal conductive paste for base layers being Cu powder, an amount of Ni powder of the metal conductive paste for base layers being 1 wt % or more and 5.0 wt % or less on a presumption that an amount of Cu is 100 wt %; and firing the metal conductive pastes for base layers. 9. The method as claimed in claim 8 , wherein a temperature of the firing of the metal conductive pastes for base layers is 780° C. or more and 860° C. or less. 10. The method as claimed in claim 8 , wherein an average particle diameter of the Ni powder is 0.1 μm or more and 5 μm or less in the metal conductive pastes for the base layers. 11. The method as claimed in claim 8 , wherein an average particle diameter of the Cu powder is 0.5 μm or more and 10 μm or less in the metal conductive pastes for the base layers. 12. The method as claimed in claim 8 , wherein the amount of Ni powder of the metal conductive paste for base layers is 3 wt % or more on a presumption that the amount of Cu is 100 wt %. 13. The method as claimed in claim 8 , wherein the amount of Ni powder of the metal conductive paste for base layers is 5 wt % or more on a presumption that the amount of Cu is 100 wt %. 14. The method as claimed in claim 8 , wherein the amount of Ni powder of the metal conductive paste for base layers is 7 wt % or less on a presumption that the amount of Cu is 100 wt %. 15. A ceramic electronic component device: a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being Ni, the internal electrode layers being alternately exposed to two end faces of the multilayer chip opposite to each other; and external electrodes, each of which is provided on each of the two end faces, wherein each of the external electrodes includes a base layer contacting the internal electrode layers, a main component of the base layer being Cu, and wherein the base layer includes Ni of 1 wt % or more and 10 wt % or less on a presumption that an amount of Cu is 100 wt %, and the base layer includes an oxide including Ni and Zn. 16. The ceramic electronic device as claimed in claim 15 , wherein an average grain diameter of the oxide including the Ni and the Zn is 1 μm or less, in the base layer. 17. A manufacturing method of a ceramic electronic device comprising: preparing a ceramic multilayer structure having a substantially rectangular parallelepiped shape in which dielectric green sheets including a main component ceramic and metal conductive pastes for internal electrode layers including Ni as a main component metal are alternately stacked, the metal conductive pastes being alternately exposed to two end faces of the ceramic multilayer structure opposite to each other; forming a multilayer chip by firing the ceramic multilayer structure; providing metal conductive pastes for base layers contacting the two end faces, a main component metal of the metal conductive paste for base layers being Cu powder, an amount of Ni powder of the metal conductive paste for base layers being 1 wt % or more and 10 wt % or less on a presumption that an amount of Cu is 100 wt %; and firing the metal conductive pastes for base layers; wherein the base layer includes an oxide including Ni and Zn. 18. The ceramic electronic device as claimed in claim 17 , wherein an average grain diameter of the oxide including the Ni and the Zn is 1 μm or less, in the base layer.

Assignees

Inventors

Classifications

  • H01G4/30Primary

    Stacked capacitors (H01G4/33 takes precedence) · CPC title

  • the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence) · CPC title

  • Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

  • H01G4/2325Primary

    characterised by the material of the terminals · CPC title

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What does patent US12112893B2 cover?
A ceramic electronic component includes a multilayer chip having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, a main component of the dielectric layers being ceramic, a main component of the internal electrode layers being Ni, the internal electrode layers being alternately exposed to two end faces o…
Who is the assignee on this patent?
Taiyo Yuden Kk
What technology area does this patent fall under?
Primary CPC classification H01G4/30. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 08 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 7 related publications on this page (citations in our corpus or others sharing the same primary CPC).