Reflective display mirror hinge memory reduction systems and methods

Patent metadata

Field	Value
Publication number	US-12112715-B2
Application number	US-202318353622-A
Country	US
Kind code	B2
Filing date	Jul 17, 2023
Priority date	Sep 21, 2022
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A device may include an electronic display to display image frames. The display may include illuminators that generate light and mirrors that selectively direct the light to pixel locations based bitplanes that set the arrangement of the mirrors. Additionally, the device may include duty cycle balancing circuitry that generates and provides duty cycle balancing signals to the electronic display. In response to the duty cycle balancing signals, the electronic display is implements balancing on bitplanes during at least a first portion of off periods during the image frames and implements balancing off bitplanes during at least a second portion of the off periods such that, in the aggregate, a ratio of respective on times of the mirrors to respective off times of the mirrors is balanced across the image frames during the off periods.

First claim

What is claimed is:

1. An electronic device comprising:
an electronic display configured to display a plurality of image frames, wherein the electronic display comprises:
one or more illuminators configured to generate light during emission periods of the plurality of image frames; and
a plurality of mirrors configured to selectively direct the light to a plurality of pixel locations of the electronic display based on a plurality of bitplanes, wherein each bitplane of the plurality of bitplanes sets an arrangement of the plurality of mirrors; and

duty cycle balancing circuitry configured to generate and provide duty cycle balancing signals to the electronic display, wherein, in response to the duty cycle balancing signals, the electronic display is configured to implement balancing on bitplanes during at least a first portion of off periods of the plurality of image frames and balancing off bitplanes during at least a second portion of the off periods of the plurality of image frames such that, in an aggregate, a ratio of respective on times of the plurality of mirrors to respective off times of the plurality of mirrors is balanced across the plurality of image frames during the off periods.

2. The electronic device of claim 1 , wherein the balancing on bitplane is configured to set the arrangement of the plurality of mirrors such that each mirror of the plurality of mirrors is in an on position, and wherein the balancing off bitplane is configured to set the arrangement of the plurality of mirrors such that each mirror of the plurality of mirrors is in an off position.

3. The electronic device of claim 1 , wherein implementing the balancing on bitplanes during the first portion of the off periods of the plurality of image frames comprises implementing a balancing on bitplane during a first off period of a first image frame of the plurality of image frames, and wherein implementing the balancing off bitplanes during the second portion of the off periods of the plurality of image frames comprises implementing a balancing off bitplane during a second off period of a second image frame of the plurality of image frames different from the first image frame.

4. The electronic device of claim 1 , wherein the electronic device comprises one or more light attenuators, wherein, during the emission periods, each of the plurality of mirrors are configured to selectively direct the light to a respective pixel location of the plurality of pixel locations or to a light attenuator of the one or more light attenuators.

5. The electronic device of claim 1 , comprising image processing circuitry configured to provide the plurality of bitplanes to the plurality of mirrors via a bitplane datalink.

6. The electronic device of claim 5 , wherein the image processing circuitry comprises the duty cycle balancing circuitry, and wherein the duty cycle balancing signals comprise the balancing on bitplanes and the balancing off bitplanes provided via the bitplane datalink.

7. The electronic device of claim 5 , wherein the duty cycle balancing signals comprise display commands that are not provided via the bitplane datalink.

8. The electronic device of claim 1 , wherein the one or more illuminators comprise one or more light emitting diodes (LEDs).

9. The electronic device of claim 1 , wherein each image frame of the plurality of image frames is divided into a single emission period and a single off period.

10. The electronic device of claim 9 , wherein implementing the balancing on bitplanes during the first portion of the off periods of the plurality of image frames and implementing the balancing off bitplanes during the second portion of the off periods of the plurality of image frames comprises:
implementing a balancing off bitplane at a beginning of the single off period and implementing a balancing on bitplane at a midpoint of the single off period; or
implementing the balancing on bitplane at the beginning of the single off period and implementing the balancing off bitplane at the midpoint of the single off period.

11. A method comprising:
supplying a balancing off bitplane to a plurality of mirrors during a first off period of a first image frame, wherein the balancing off bitplane is configured to set each of the plurality of mirrors to an off position; and
supplying a balancing on bitplane to the plurality of mirrors during a second off period of a second image frame, wherein the balancing on bitplane is configured to set each of the plurality of mirrors to an on position, wherein, in an aggregate of the first off period and the second off period, a first amount of time that the plurality of mirrors are in the off position is balanced by a second amount of time that the plurality of mirrors are in the on position.

12. The method of claim 11 , comprising:
supplying, via duty cycle balancing circuitry, a reset command to a display panel, wherein, in response to the reset command, the display panel is configured to supply the balancing off bitplane to the plurality of mirrors; and
supplying, via the duty cycle balancing circuitry, a set command to the display panel, wherein, in response to the set command, the display panel is configured to supply the balancing on bitplane to the plurality of mirrors.

13. The method of claim 11 , comprising generating, via duty cycle balancing circuitry, the balancing off bitplane and the balancing on bitplane.

14. The method of claim 13 , wherein the balancing off bitplane and the balancing on bitplane are supplied from the duty cycle balancing circuitry to the plurality of mirrors via a bitplane datalink.

15. The method of claim 11 , wherein the first image frame comprises a first emission period corresponding to first light emissions that aggregate to form a first image of the first image frame, and wherein the second image frame comprises a second emission period corresponding to second light emissions that aggregate to form a second image of the first image frame.

16. An electronic display comprising:
a plurality of illuminators configured to generate light during emission periods of image frames and to not generate light during off periods of the image frames;
a plurality of mirrors configured to selectively articulate to either an on position or an off position, wherein the on position of a mirror of the plurality of mirrors directs the light, if generated, to a pixel location of a plurality of pixel locations, and wherein the off position of the mirror directs the light, if generated, to a light attenuator; and
a bitplane datalink configured to receive a first plurality of image data bitplanes of a first image frame and a second plurality of image data bitplanes of a second image frame, wherein the plurality of mirrors are configured to selectively articulate during the emission periods of the first image frame and the second image frame according to the first plurality of image data bitplanes and the second plurality of image data bitplanes, respectively, and wherein, during the off periods of the first image frame and the second image frame, each of the plurality of mirrors is configured to articulate to the off position in response to a balancing off bitplane and articulate to the on position in response to a balancing on bitplane, wherein, in an aggregate of the off periods of the first image frame and the second image frame, a first amount of time that the plurality of mirrors are in the off position is balanced by a second amount of time that the plurality of mirrors are in the on position.

17. The electronic display of claim 16 , wherein the balancing

Assignees

• Apple Inc

Inventors

• Darmon Denis M
• Jeon Kanghoon
• Dominguez-Caballero Jose A
• Wang Bilin

Classifications

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2370/00

  Aspects of data communication · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0626

  for control of overall brightness · CPC title

• G02B26/0833 Primary

  the reflecting element being a micromechanical device, e.g. a MEMS mirror, DMD (G02B26/0825 takes precedence; micromechanical devices in general B81B) · CPC title