Display panel and display device

Patent metadata

Field	Value
Publication number	US-12112708-B2
Application number	US-202318198013-A
Country	US
Kind code	B2
Filing date	May 16, 2023
Priority date	Jan 8, 2021
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A display panel includes a pixel circuit and a driving circuit. The pixel circuit includes a driving transistor. The driving circuit is configured to provide a signal for the pixel circuit, receive a third voltage signal and a fourth voltage signal, and generate an output signal. The third voltage signal is a high-level signal, and the fourth voltage signal is a low-level signal. A working process of the pixel circuit includes a reset phase and a bias phase. The output signal of the driving circuit is a reset signal in the reset phase. The output signal of the driving circuit is a bias signal in the bias phase. In response to the driving transistor being a PMOS transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal.

First claim

What is claimed is:

1. A display panel, comprising:
a pixel circuit, including a driving transistor; and
a driving circuit, configured to provide a signal for the pixel circuit, receive a third voltage signal and a fourth voltage signal, and generate an output signal, the third voltage signal being a high-level signal, and the fourth voltage signal being a low-level signal;
wherein:
a working process of the pixel circuit includes a reset phase and a separate bias phase;
the output signal of the driving circuit is a reset signal in the reset phase;
the output signal of the driving circuit is a bias signal in the bias phase; and
in response to the driving transistor being a P-type transistor, the reset signal is the fourth voltage signal, and the bias signal is the third voltage signal; or
in response to the driving transistor being an N-type transistor, the reset signal is the third voltage signal, and the bias signal is the fourth voltage signal.

2. The display panel according to claim 1 , wherein the pixel circuit includes:
a data writing module, connected to a source of the driving transistor;
a compensation module, connected between a gate and a drain of the driving transistor;
a reset module, connected to the drain of the driving transistor;
wherein:
in the reset phase, the reset module and the compensation module are both turned on and the gate of the driving transistor receives the reset signal; and
in the bias phase, the reset module is turned on and the compensation module is turned off and the drain of the driving transistor receives the bias signal.

3. The display panel according to claim 1 , wherein:
the driving circuit includes N levels of shift registers cascaded with each other, N≥2; and
a shift register of the N levels of shift registers incudes:
a first control unit, configured to receive an input signal and control a signal of a first node in response to a first clock signal;
a second control unit, configured to receive a first voltage signal and control a signal of a second node in response to the input signal and the first clock signal;
a third control unit, configured to receive the first voltage signal and a second voltage signal and control a signal of a fourth node in response to the signal of the second node and a signal of a third node, wherein the third node is connected to the first node, the first voltage signal is a high-level signal and the second voltage signal is a low-level signal; and
a fourth control unit, configured to receive the third voltage signal and the fourth voltage signal and generate the output signal in response to the signal of the first node and the signal of the fourth node.

4. The display panel according to claim 3 , wherein:
the first control unit includes a seventh transistor, a source of the seventh transistor being connected to the input signal, a drain of the seventh transistor being connected to the first node, and a gate of the seventh transistor being connected to the first clock signal; and
the second control unit includes:
an eighth transistor, a source of the eighth transistor being connected to the first clock signal, a drain of the eighth transistor being connected to the second node, and a gate of the eighth transistor being connected to a fifth node;
a ninth transistor, a source of the ninth transistor being connected to the first voltage signal, a drain of the ninth transistor being connected to the fifth node, and a gate of the ninth transistor being connected to the input signal; and
a tenth transistor, a source of the tenth transistor being connected to the first voltage signal, a drain of the tenth transistor being connected to the second node, and a gate drain of the tenth transistor being connected to a first node.

5. The display panel according to claim 3 , wherein the second control unit further includes:
a fifth capacitor, a first electrode plate of the fifth capacitor being connected to the first clock signal, and a second electrode plate of the fifth capacitor being connected to a fifth node.

6. The display panel according to claim 5 , wherein the fourth control unit includes:
a first capacitor, a first electrode plate of the first capacitor being connected to the third voltage signal, a second electrode plate of the first capacitor being connected to the fourth node; and
a second capacitor, a first electrode plate of the second capacitor being connected to the fourth voltage signal, a second electrode plate of the second capacitor being connected to the second node; or
the first capacitor, the first electrode plate of the first capacitor being connected to the third voltage signal, the second electrode plate of the first capacitor being connected to the second node; and
the second capacitor, the first electrode plate of the second capacitor being connected to the fourth voltage signal, the second electrode plate of the second capacitor being connected to the fourth node.

7. The display panel according to claim 6 , wherein:
a capacitance of the first capacitor is greater than a capacitance of the fifth capacitor; and
a capacitance of the second capacitor is greater than the capacitance of the fifth capacitor.

8. The display panel according to claim 6 , wherein the third control unit includes:
a third capacitor, a first electrode plate of the third capacitor being connected to the third node, and a second electrode plate of the third capacitor being connected to the fourth node; and
a fourth capacitor, a first electrode of the fourth capacitor being connected to the second node, and a second electrode plate of the fourth capacitor being connected to the first voltage signal.

9. The display panel according to claim 8 , wherein:
a capacitance of the first capacitor is greater than a capacitance of the fourth capacitor; and/or
the capacitance of the fourth capacitor is greater than a capacitance of the fifth capacitor; and/or
a capacitance of the second capacitor is greater than a capacitance of the third capacitor; and/or
the capacitance of the third capacitor is greater than the capacitance of the fifth capacitor.

10. The display panel according to claim 3 , wherein the third control unit includes:
a third transistor, a source of the third transistor being connected to the second voltage signal, a drain of the third transistor being connected to the fourth node, and a gate of the third transistor being connected to the third node; and
a fourth transistor, a source of the fourth transistor being connected to the first voltage signal, a drain of the fourth transistor being connected to the fourth node, and a gate of the fourth transistor being connected to the second node.

11. The display panel according to claim 10 , wherein the shift register further includes:
a fifth transistor, a source of the fifth transistor being connected to the first voltage signal, a drain of the fifth transistor being connected to the source of the fourth transistor, and a gate of the fifth transistor being connected to the second node; and
a sixth transistor, a source of the sixth transistor being connected to the second voltage signal, a drain of the sixth transistor being connected to the source of the fourth transistor, and a gate of the sixth transistor being connected to the fourth node.

12. The display panel according to claim 10 , wherein the fourth control unit includes:
a first transistor and a second transistor, one of the first transistor and the second transistor responding to the signal of the fourth node, and the other one of the first transistor and the second transistor responding to the signal of the second node to control the output signal.

Assignees

• Xiamen Tianma Micro Electronics Co Ltd

Inventors

• Lai Qingjun
• Zhu Yihua
• Yuan Yong
• An Ping
• Cao Zhaokeng

Classifications

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G11C19/20

  using discharge tubes (G11C19/14 takes precedence) · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title