Machine code instruction

Patent metadata

Field	Value
Publication number	US-12112164-B2
Application number	US-202318176034-A
Country	US
Kind code	B2
Filing date	Feb 28, 2023
Priority date	Mar 1, 2022
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A processing device comprising a plurality of operand registers, wherein a first subset of the operand registers are configured to store state information for a plurality of bins, comprising a range of values and a bin count associated with each respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for each of the floating-point values: identify based on an exponent of the respective floating-point value, each one of the plurality of bins for which the respective floating-point value falls within the associated range of values; and increment the bin count associated with the identified bins.

First claim

The invention claimed is:

1. A processing device comprising:
a plurality of operand registers, wherein a first subset of the operand registers is configured to store state information for a plurality of bins, wherein for each of the plurality of bins, the state information comprises a range of values and a bin count associated with a respective bin, wherein a second subset of the operand registers is configured to store a vector of floating-point values; and
an execution unit configured to execute a first instruction taking the state information for the plurality of bins and the vector of floating-point values as operands, and in response to execution of the first instruction, for a first floating-point value of the vector:
identify, based on an exponent of the first floating-point value, a first bin of the plurality of bins for which the first floating-point value falls within an associated range of values for the first bin; and
increment a first bin count associated with the first bin.

2. The processing device of claim 1 , wherein the execution unit is further configured, in response to execution of the first instruction:
identify, based on an exponent of a second floating-point value of the vector, a second bin of the plurality of bins for which the second floating-point value falls within an associated range of values for a second bin; and
increment a second bin count associated with the second bin.

3. The processing device of claim 2 , wherein the processing device is further configured to generate a histogram from bin count statistics for the plurality of bins, the bin count statistics including the first bin count and the second bin count.

4. The processing device of claim 1 , wherein identifying the first bin comprises selecting each bin of the plurality of bins, and for each bin, implementing comparison circuitry to compare the exponent of the first floating-point value with a condition defining a respective associated range of values of each bin.

5. The processing device of claim 4 , wherein the state information for the first bin comprises a sign indicator for the first bin, and wherein the execution unit further comprises sign check circuitry to compare a sign of the first floating-point value with the sign indicator of the first bin, wherein the associated range of values of the first bin comprises only values matching the sign indicator of the first bin.

6. The processing device of claim 4 , wherein the execution unit is further configured, in response to execution of the first instruction, to identify whether each of a plurality of floating-point values fall within the respective associated ranges of values for each of the plurality of bins in parallel.

7. The processing device of claim 1 , wherein, for the first bin, the state information comprises a threshold exponent field and wherein the execution unit is configured to, for the first floating-point value, perform identification of the first bin in dependence upon a value of the threshold exponent field for the first bin.

8. The processing device of claim 1 , wherein a threshold bin count saturation value is defined, and wherein the execution unit is configured, in response to the execution of the first instruction, for the first bin, to compare the first bin count to the threshold bin count saturation value, and to identify the first bin from among an unsaturated subset of bins for which the first floating-point value falls within the associated range of values, the unsaturated subset of bins comprising bins having a bin count less than the threshold bin count saturation value.

9. The processing device of claim 1 , wherein the state information for each bin comprises at least one mode indicator, and wherein the execution unit comprises bin check circuitry, wherein the bin check circuitry is configured to identify the associated range of values for the first bin based on a value of the mode indicator for the first bin.

10. The processing device of claim 9 , wherein the at least one mode indicator comprises an item selected from a list consisting of: a threshold exponent field and a threshold range field.

11. The processing device of claim 10 , wherein the at least one mode indicator indicates a default mode, and wherein a lower limit of the associated range of values is a value of the threshold exponent field, and an upper limit of the range of values is a sum of the value of the threshold exponent field and a value of the threshold range field.

12. The processing device of claim 9 , wherein the at least one mode indicator indicates a first special mode, and the associated range of values for the first bin comprises either zero or a range of denormalized values.

13. The processing device of claim 12 , wherein the at least one mode indicator comprises a threshold exponent field, and wherein the first special mode is indicated by a special value of the threshold exponent field.

14. The processing device of claim 13 , wherein the at least one mode indicator further comprises a threshold range field having a value of zero, wherein the associated range of values for the first bin comprises zero only.

15. The processing device of claim 12 , wherein the at least one mode indicator further comprises a threshold range field having a value that is non-zero, and the associated range of values for the first bin comprises the range of denormalized values.

16. The processing device of claim 9 , wherein the at least one mode indicator indicates a second special mode, and the associated range of values for the first bin comprises all values less than or equal to a threshold for the first bin.

17. The processing device of claim 9 , wherein the at least one mode indicator indicates a third special mode, and the associated range of values for the first bin comprises all values greater than or equal to a threshold for the first bin.

18. The processing device of claim 17 , wherein the at least one mode indicator comprises a threshold range field, and wherein the third special mode is indicated by a value of the threshold range field.

19. The processing device of claim 1 , wherein the execution unit is further configured to process gradients of a machine intelligence application, the gradients scaled by a loss scaling factor, wherein the first instruction is executed by the execution unit for each of a plurality of vectors of the gradients to generate a histogram comprising a second plurality of bins, inclusive of the plurality of bins, and wherein the loss scaling factor is adjusted based on a relative count of a subset of the plurality of bins relative to a total count of all bins of the second plurality of bins.

20. The processing device of claim 1 , wherein the first subset of the operand registers and the second subset of the operand registers are included in an arithmetic register file.

21. The processing device of claim 1 , wherein the floating-point values of the vector are provided in one of:
a thirty-two bit representation;
a sixteen bit representation; or
an eight-bit representation.

22. The processing device of claim 1 , wherein, in response to the execution of the first instruction, where the first floating-point value is a subnormal floating-point value, the execution unit is further configured to:
identify a second bin of the plurality of bins for which zero falls within the associated range of values for the second bin, and increment a second bin count associated with the second bin; or
identify a third bin of the p

Assignees

• Graphcore Ltd

Inventors

• Alexander Alan
• Knowles Simon
• Da Costa Godfrey
• Noune Badreddine

Classifications

• G06F2207/382

  Reconfigurable for different fixed word lengths · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F9/30014 Primary

  with variable precision · CPC title

• G06F7/24 Primary

  Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers {sorting methods in general}(G06F7/36 takes precedence) · CPC title

• G06F7/483 Primary

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title