Jammer detection system

Patent metadata

Field	Value
Publication number	US-12107673-B2
Application number	US-202117468281-A
Country	US
Kind code	B2
Filing date	Sep 7, 2021
Priority date	Sep 7, 2021
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

Certain aspects of the present disclosure generally relate to jamming detection for radio frequency (RF) front-end circuitry. For example, certain aspects provide an apparatus having a first counter configured to count a number of times that a power of a reception signal exceeds a first threshold. The apparatus also includes a second counter configured to count a number of measurements of the power of the reception signal. The apparatus further includes control logic having a first input coupled to an output of the first counter and having a second input coupled to an output of the second counter. The control logic is configured to determine an amount of jamming over a measurement window based on the number of times that the power of the reception signal exceeds the first threshold and on the number of measurements.

First claim

What is claimed is:

1. An apparatus for wireless communications, the apparatus comprising:
a jamming detection circuit disposed prior to an analog baseband filter, the jamming detection circuit comprising:
a first counter configured to count a number of times that a power of a reception signal exceeds a first threshold;
a second counter configured to count a number of measurements of the power of the reception signal; and
control logic having a first input coupled to an output of the first counter and having a second input coupled to an output of the second counter, the control logic being configured to:
obtain a first plurality of counter values of the first counter and a second plurality of counter values of the second counter, each counter value of the first plurality of counter values indicating a respective number of times that the power of the reception signal exceeds the first threshold during a respective time interval of a measurement window, and each counter value of the second plurality of counter values indicating a respective number of measurements of the power of the reception signal during the respective time interval of the measurement window;
determine at least one of the respective time intervals is associated with at least one of (i) a transition from a first type of transmit beam to a second type of transmit beam for the reception signal or (ii) a transition from a first gain state to a second gain state for the reception signal;
responsive to the determination, determine an amount of jamming over the measurement window based on a subset of the first plurality of counter values and on a subset of the second plurality of counter values, wherein at least one of the subset of the first plurality of counter values is smaller than the first plurality of counter values or the subset of the second plurality of counter values is smaller than the second plurality of counter values; and
adjust an analog gain of an amplifier based on the amount of jamming.

2. The apparatus of claim 1 , wherein the control logic is configured to determine the amount of jamming by dividing (i) a sum of the subset of the first plurality of counter values by (ii) a sum of the subset of the second plurality of counter values.

3. The apparatus of claim 1 , wherein the amount of jamming comprises at least one of: (i) an amount of time that jamming occurs over the measurement window or (ii) a percentage of jamming over the measurement window.

4. The apparatus of claim 1 , wherein the jamming detection circuit further comprises a power detector circuit having an output coupled to an input of the first counter, the power detector circuit being configured to determine the power of the reception signal.

5. The apparatus of claim 4 , further comprising the amplifier, wherein the amplifier has an output coupled to an input of the power detector circuit, wherein the control logic is configured to generate a logic signal to adjust the analog gain of the amplifier based on the amount of jamming.

6. The apparatus of claim 5 , further comprising:
a frequency synthesizer; and
a mixer having a first input coupled to the output of the amplifier, having a second input coupled to an output of the frequency synthesizer, and having an output coupled to the input of the power detector circuit.

7. The apparatus of claim 5 , wherein the logic signal is configured to trigger a reduction of the analog gain when the amount of jamming exceeds a second threshold.

8. The apparatus of claim 5 , wherein the logic signal is configured to trigger an increase of the analog gain when the amount of jamming is below a second threshold.

9. The apparatus of claim 4 , wherein the jamming detection circuit further comprises a comparator having an input coupled to the output of the power detector circuit and having an output coupled to the input of the first counter, the comparator being configured to compare the power of the reception signal to the first threshold and output a digital signal based on the comparison.

10. The apparatus of claim 1 , wherein the control logic is further configured to:
schedule a command to latch at least a first counter value of the first plurality of counter values and a second counter value of the second plurality of counter values at a first time instance based on an absolute system time; and
read the latched first counter value and the latched second counter value at a second time instance subsequent to the first time instance based on the absolute system time.

11. A wireless device comprising the apparatus of claim 1 , the wireless device further comprising:
at least one antenna;
an analog-to-digital converter (ADC); and
a receive path coupled between the at least one antenna and the ADC and comprising the analog baseband filter, a portion of the receive path being configured to generate the reception signal.

12. The wireless device of claim 11 , wherein the first counter and the second counter are configured to be clocked by a same clock signal and wherein the second counter is configured to increment the number of measurements by one for each rising edge or each falling edge of the clock signal, at least while the portion of the receive path is activated.

13. The apparatus of claim 1 , wherein:
the control logic is further configured to discard at least one of the first plurality of counter values and at least one of the second plurality of counter values associated with the at least one of the respective time intervals associated with the at least one of (i) the transition from the first type of transmit beam to the second type of transmit beam for the reception signal or (ii) the transition from the first gain state to the second gain state for the reception signal;
the subset of the first plurality of counter values lacks the discarded at least one of the first plurality of counter values; and
the subset of the second plurality of counter values lacks the discarded at least one of the second plurality of counter values.

14. A method for wireless communications, the method comprising:
prior to filtering a reception signal via an analog baseband filter:
determining a power of the reception signal;
counting, with a first counter, a number of times that the power of the reception signal exceeds a first threshold;
counting, with a second counter, a number of measurements of the power of the reception signal;
obtaining a first plurality of counter values of the first counter and a second plurality of counter values of the second counter, each counter value of the first plurality of counter values indicating a respective number of times that the power of the reception signal exceeds the first threshold during a respective time interval of a measurement window, and each counter value of the second plurality of counter values indicating a respective number of measurements of the power of the reception signal during the respective time interval of the measurement window;
determining at least one of the respective time intervals is associated with at least one of (i) a transition from a first type of transmit beam to a second type of transmit beam for the reception signal or (ii) a transition from a first gain state to a second gain state for the reception signal;
responsive to the determination, determining an amount of jamming over the measurement window based on a subset of the first plurality of counter values and on a subset of the second plurality of counter values, wherein at least one of the subset of the first plurality of counter values is smaller than the first plurality of counter values or the subset of the second plurality of

Assignees

• Qualcomm Inc

Inventors

• Shah Peter
• Kanetkar Ajay Devadatta
• Ekbatani Siavash
• Yu Yuanning
• Patel Shrenik
• Qiao Dongjiang
• Rangarajan Rajagopalan

Classifications

• H04K3/45

  characterized by including monitoring of the target or target signal, e.g. in reactive jammers or follower jammers for example by means of an alternation of jamming phases and monitoring phases, called "look-through mode" · CPC title

• H04K3/224

  with countermeasures at transmission and/or reception of the jammed signal, e.g. stopping operation of transmitter or receiver, nulling or enhancing transmitted power in direction of or at frequency of jammer · CPC title

• H04K3/22 Primary

  including jamming detection and monitoring · CPC title

• H04B17/318

  Received signal strength · CPC title