Digital-to-analog converter circuit

Patent metadata

Field	Value
Publication number	US-12107591-B2
Application number	US-202218054333-A
Country	US
Kind code	B2
Filing date	Nov 10, 2022
Priority date	Nov 29, 2021
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

In accordance with an embodiment, a digital-to-analog converter (DAC) includes: a W-2W current mirror that includes a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, where ones of the second plurality of MOS transistors are coupled between drains of adjacent ones of the first plurality of MOS transistors; and a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

First claim

What is claimed is:

1. A circuit, comprising:
a diode-connected MOS transistor having a drain terminal connected to an input node and source terminal connected to a reference voltage node, the diode-connected MOS transistor being configured to pass a reference current from the input node to the reference voltage node;
a plurality of ordered mirroring MOS transistors having respective gate terminals connected to a gate terminal of the diode-connected MOS transistor and respective drain terminals alternatively couplable either to a first current node or to a second current node as a function of a plurality of respective ordered control signals, wherein a first mirroring MOS transistor in the plurality of ordered mirroring MOS transistors has a source terminal directly connected to the reference voltage node; and
a plurality of current control MOS transistors having respective gate terminals connected to the gate terminal of the diode-connected MOS transistor, wherein each current control MOS transistor is arranged between source terminals of two consecutive mirroring MOS transistors in the plurality of ordered mirroring MOS transistors, wherein
the diode-connected MOS transistor and the plurality of ordered mirroring MOS transistors all have the same channel dimensions,
the plurality of current control MOS transistors all have the same channel dimensions,
channels of the plurality of current control MOS transistors have a same length and twice a width of a channel of the diode-connected MOS transistor, and
mirroring MOS transistors of the plurality of ordered mirroring MOS transistors whose source terminals are not directly connected to the reference voltage node have respective bulk terminals configured to receive one or more compensation signals, the one or more compensation signals having respective values that decrease with increasing temperature.

2. The circuit of claim 1 , wherein the one or more compensation signals are linearly dependent on temperature.

3. The circuit of claim 1 , further comprising a compensation circuit configured to produce the one or more compensation signals, the compensation circuit comprising:
an inversely proportional-to-absolute-temperature current generator arrangement configured to produce a compensation voltage signal that decreases linearly as a function of increasing temperature;
a voltage divider circuit; and
a buffer stage configured to supply the compensation voltage signal to the voltage divider circuit,
wherein the one or more compensation signals are produced at one or more intermediate nodes of the voltage divider circuit.

4. The circuit of claim 3 , wherein the inversely proportional-to-absolute-temperature current generator arrangement comprises:
a first p-channel MOS transistor and a first n-channel MOS transistor arranged in series between a supply voltage node and the reference voltage node; and
a second p-channel MOS transistor and a second n-channel MOS transistor arranged in series between the supply voltage node and the reference voltage node, wherein
the first n-channel MOS transistor has a source terminal coupled to the reference voltage node, a drain terminal coupled to a drain terminal of the first p-channel MOS transistor, and a gate terminal configured to receive a bandgap reference voltage,
the first p-channel MOS transistor has a source terminal coupled to the supply voltage node and a gate terminal coupled to its drain terminal,
the second p-channel MOS transistor has a source terminal coupled to the supply voltage node, a drain terminal coupled to a drain terminal of the second n-channel MOS transistor, and a gate terminal coupled to the gate terminal of the first p-channel MOS transistor,
the second n-channel MOS transistor has a source terminal coupled to the reference voltage node and a gate terminal coupled to its drain terminal, and
the compensation voltage signal is produced at the gate terminal of the second n-channel MOS transistor.

5. The circuit of claim 3 , wherein the buffer stage comprises an amplifier circuit having an output terminal coupled to the voltage divider circuit, a non-inverting input terminal configured to receive the compensation voltage signal, and an inverting input terminal coupled to its output terminal.

6. The circuit of claim 1 , wherein the mirroring MOS transistors of the plurality of ordered mirroring MOS transistors whose source terminals are not directly connected to the reference voltage node include triple-well n-channel MOS transistors.

7. The circuit of claim 1 , wherein a source terminal of a last mirroring MOS transistor in the plurality of ordered mirroring MOS transistors is directly connected to a source terminal of a second-to-last mirroring MOS transistor in the plurality of ordered mirroring MOS transistors.

8. The circuit of claim 7 , wherein the last mirroring MOS transistor and the second-to-last mirroring MOS transistor have respective bulk terminals configured to receive a same compensation signal.

9. The circuit of claim 1 , wherein a drain terminal of a last mirroring MOS transistor in the plurality of ordered mirroring MOS transistors and a drain terminal of a second-to-last mirroring MOS transistor in the plurality of ordered mirroring MOS transistors are steadily coupled to the second current node.

10. The circuit of claim 1 , wherein the drain terminals of the plurality of ordered mirroring MOS transistors are alternatively couplable to the first current node or to the second current node via respective switches activatable as a function of the respective ordered control signals.

11. The circuit of claim 1 , wherein the diode-connected MOS transistor, the plurality of ordered mirroring MOS transistors and the plurality of current control MOS transistors include n-channel transistors.

12. The circuit of claim 1 , further comprising a first output diode-connected MOS transistor having a drain terminal connected to the first current node and source terminal connected to a supply voltage node, and a second output diode-connected MOS transistor having a drain terminal connected to the second current node and a source terminal connected to the supply voltage node.

13. A digital-to-analog converter (DAC) comprising:
a W-2W current mirror comprising a first plurality of MOS transistors having a first width, and second plurality of MOS transistors having a second width that is twice the first width, wherein ones of the second plurality of MOS transistors are coupled between drains of adjacent ones o the first plurality of MOS transistors; and
a bulk bias generator having a plurality of output nodes coupled to corresponding bulk nodes of the first plurality of MOS transistors, wherein the plurality of output nodes are configured to provide voltages that are inversely proportional to temperature.

14. The DAC of claim 13 , further comprising an output coupling network coupled to output nodes of the first plurality of MOS transistors, the output coupling network configured to selectively couple the output nodes of the first plurality of MOS transistors to an output node of the DAC in accordance with a digital DAC input word.

15. The DAC of claim 13 , wherein the bulk bias generator comprises:
a voltage generator configured to provide an inversely proportional to temperature reference voltage; and
a resistor ladder coupled to an output of the voltage generator, the resistor ladder comprising a plurality of taps, wherein output nodes of the plurality of output nodes of the bulk bias generator are coupled to corresponding taps of the plurality of taps.

16. The DAC of claim

Assignees

• St Microelectronics Srl

Inventors

• Maccarrone Agatino Massimo
• Conte Antonino
• Tomaiuolo Francesco
• Pisasale Michelangelo
• Ruta Marco

Classifications

• H03M1/78

  using ladder network · CPC title

• H03M1/745

  with weighted currents · CPC title

• H03M1/0604 Primary

  at one point, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/089 Primary

  of temperature variations · CPC title