BD PWM modulation circuit for use in class D amplifier and modulation method thereof

Patent metadata

Field	Value
Publication number	US-12107586-B2
Application number	US-202217681728-A
Country	US
Kind code	B2
Filing date	Feb 26, 2022
Priority date	Mar 18, 2021
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

A BD type pulse width modulation (PWM) circuit is configured to convert a pair of complementary input signals to a pair of output PWM signals. The BD PWM circuit modulates a basic modulation signal according to the pair of input signals, to generate a basic PWM signal. The common mode levels of the pair of input signals and the basic modulation signal are the same. The BD PWM circuit modulates an offset modulation signal according to the pair of input signals to generate an offset PWM signal. The offset modulation signal and the basic modulation signal have a non-zero offset in between. The BD PWM circuit selects the offset PWM signal or a heavy load PWM signal as the pair of output PWM signals. The heavy load PWM signal is correlated with the basic PWM signal.

First claim

What is claimed is:

1. A BD type pulse width modulation (PWM) circuit for use in a class D amplifier, which is configured to operably convert a pair of complementary input signals to a pair of output PWM signals; the BD PWM circuit comprising:
a duty ratio adjustment circuit, which is configured to operably generate a plurality of intermediate PWM signals, wherein the plurality of intermediate PWM signals include: a basic PWM signal, an offset PWM signal and a heavy load PWM signal, wherein each intermediate PWM signal correspondingly has an in-phase sub-signal, a reversed-phase sub-signal and a differential mode signal, wherein the differential mode signal is a difference between the in-phase sub-signal and the reversed-phase sub-signal, wherein the duty ratio adjustment circuit includes:
a basic comparison circuit, which is configured to operably modulate a basic modulation signal according to the pair of input signals, to generate the basic PWM signal, wherein a common mode level of the pair of input signals is the same as a common mode level of basic modulation signal; and
an offset comparison circuit, which is configured to operably modulate an offset modulation signal according to the pair of input signals, to generate the offset PWM signal, wherein the offset modulation signal and the basic modulation signal have a non-zero offset in between;

a load detection circuit, which is configured to operably determine whether levels of the pair of input signals are lower than a light load threshold according to the offset PWM signal, wherein when the levels of the pair of input signals are lower than the light load threshold, a light load signal is enabled; and
an output selection circuit, which is configured to operably select the offset PWM signal as the pair of output PWM signals in a case when the levels of the pair of input signals are lower than the light load threshold and select the heavy load PWM signal as the pair of output PWM signals in a case when the levels of the pair of input signals are not lower than the light load threshold, so that a root-mean-square power of the pair of output PWM signals is smaller than a root-mean-square power of the basic PWM signal;
wherein the heavy load PWM signal is correlated with the basic PWM signal.

2. The BD PWM circuit of claim 1 , wherein the load detection circuit is configured to periodically determine, according to an operation period, whether the in-phase sub-signal and the reversed-phase sub-signal corresponding to the offset PWM signal both have a pulse within a previous operation period, so as to enable the light load signal accordingly, wherein the enablement of the light load signal is indicative of a case where the levels of the pair of input signals are lower than the light load threshold.

3. The BD PWM circuit of claim 1 , wherein:
the heavy load PWM signal corresponds to or is the basic PWM signal; or
the plurality of intermediate PWM signals further includes a one-side PWM signal, and the heavy load PWM signal corresponds to or is the one-side PWM signal;
wherein the duty ratio adjustment circuit further includes: a one-side selection circuit, which is configured to operably generate the in-phase sub-signal corresponding to the one-side PWM signal according to a positive value of the differential mode signal corresponding to the basic PWM signal, and to operably generate the reversed-phase sub-signal corresponding to the one-side PWM signal according to a negative value of the differential mode signal corresponding to the basic PWM signal.

4. The BD PWM circuit of claim 3 , wherein the heavy load PWM signal is the one-side PWM signal or the basic PWM signal.

5. The BD PWM circuit of claim 4 , wherein the pair of output PWM signals are configured to operably control a driver stage circuit, so as to drive two ends of a load in a pulse width modulation fashion, wherein the heavy load PWM signal is determined to be the one-side PWM signal or the basic PWM signal according to a power supply of the driver stage circuit, a level of the load, a temperature related to the class D amplifier, or an operation frequency, wherein the operation frequency corresponds to the operation period.

6. The BD PWM circuit of claim 1 , wherein a level of the offset is correlated with the light load threshold.

7. The BD PWM circuit of claim 1 , wherein each of the basic modulation signal and the offset modulation signal is configured as a triangular wave or a sawtooth wave, and wherein the basic modulation signal and the offset modulation signal are both synchronous with the operation period.

8. The BD PWM circuit of claim 7 , wherein an absolute value of a level of the offset is smaller than ½ of a peak-to-peak value of the basic modulation signal.

9. The BD PWM circuit of claim 1 , wherein:
the basic comparison circuit includes:
a first comparator, which is configured to operably compare an in-phase input signal of the pair of input signals with the basic modulation signal, so as to generate the in-phase sub-signal of the basic PWM signal; and
a second comparator, which is configured to operably compare a reversed-phase input signal of the pair of input signals with the basic modulation signal, so as to generate the reversed-phase sub-signal of the basic PWM signal; and

the offset comparison circuit includes:
a third comparator, which is configured to operably compare the in-phase input signal of the pair of input signals with the offset modulation signal, so as to generate the in-phase sub-signal of the offset PWM signal; and
a fourth comparator, which is configured to operably compare the reversed-phase input signal of the pair of input signals with the offset modulation signal, so as to generate the reversed-phase sub-signal of the offset PWM signal.

10. The BD PWM circuit of claim 2 , wherein the load detection circuit includes:
a first status circuit, which is configured to operably trigger an in-phase pulse indication signal according to the in-phase sub-signal of the offset PWM signal;
a second status circuit, which is configured to operably trigger a reversed-phase pulse indication signal according to the reversed-phase sub-signal of the offset PWM signal; and
a third status circuit, which is configured to operably determine whether the in-phase pulse indication signal and the reversed-phase pulse indication signal are both enabled according to a clock signal cycling by the operation period, so as to trigger and enable the light load signal, thereby indicating that the levels of the pair of input signals are lower than the light load threshold.

11. The BD PWM circuit of claim 3 , wherein the one-side selection circuit includes:
a first logic gate, which is configured to operably execute an AND logic operation on a reversed-phase signal of the reversed-phase sub-signal of the basic PWM signal and the in-phase sub-signal of the basic PWM signal, so as to generate the in-phase sub-signal of the one-side PWM signal; and
a second logic gate, which is configured to operably execute an AND logic operation on a reversed-phase signal of the in-phase sub-signal of the basic PWM signal and the reversed-phase sub-signal of the basic PWM signal, so as to generate the reversed-phase sub-signal of the one-side PWM signal.

12. A BD type pulse width modulation (PWM) method for use in a class D amplifier, which is configured to operably convert a pair of complementary input signals to a pair of output PWM signals; the BD PWM method comprising:
step S 1 : generating a plurality of intermediate PWM signals, wherein the plurality of intermediate PWM signals includes: a basic PWM signal, an offset PWM signal and a heavy load PWM signal,

Assignees

• Richtek Technology Corp

Inventors

• Chen Yi-Kuang
• Hsiao Ming-Jun

Classifications

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03F3/217

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F2200/351

  Pulse width modulation being used in an amplifying circuit · CPC title

• H03F3/183

  with semiconductor devices only · CPC title

• H03F3/2173

  of the bridge type · CPC title