Semiconductor device
US-2021066123-A1 · Mar 4, 2021 · US
Pattern sheet, semiconductor intermediate product, and hole etching method
US12106970B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12106970-B2 |
| Application number | US-202117919520-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 2, 2021 |
| Priority date | Apr 17, 2020 |
| Publication date | Oct 1, 2024 |
| Grant date | Oct 1, 2024 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
The present disclosure discloses a pattern sheet, a semiconductor intermediate product, and a hole etching method. The pattern sheet includes a substrate, a dielectric layer, and a mask structure. The mask structure includes a multi-layer mask layer. An uppermost mask layer is a photoresist layer. A thickness of each layer of the mask layer and etching selectivity ratios between the layers below the mask layer satisfy that in each two neighboring layers of the mask layer, a lower layer of the mask layer is etched to form a through-hole penetrating a thickness of the lower layer of the mask layer, a remaining thickness of the upper layer of the mask layer is greater than or equal to zero.
First claim
Opening claim text (preview).
What is claimed is: 1. A pattern sheet, comprising a first mask layer, a second mask layer, a dielectric layer, and a substrate sequentially arranged in stacks from top to bottom, wherein: the first mask layer includes a first hole penetrating the first mask layer along a thickness direction of the first mask layer and satisfies: d 1 × S 5 > d 2 , and d 2 ⩾ ( d 1 - d 4 / S 3 ) × S 2 / S 1 + d 4 / S 4 ; or d 1 × S 5 = d 2 , and d 2 > ( d 1 - d 4 / S 3 ) × S 2 / S 1 + d 4 / S 4 ; wherein, d1 denotes a thickness of the first mask layer, d2 denotes a thickness of the second mask layer, d4 denotes a thickness of the dielectric layer, S1 denotes an etching selectivity ratio of the substrate and the first mask layer, S2 denotes an etching selectivity ratio of the substrate and the second mask layer, S3 denotes an etching selectivity ratio of the dielectric layer and the first mask layer, S4 denotes an etching selectivity ratio of the dielectric layer and the second mask layer, and S5 denotes an etching selectivity ratio of the second mask layer and the first mask layer. 2. The pattern sheet according to claim 1 , wherein the second mask layer includes a material containing silicon. 3. The pattern sheet according to claim 2 , wherein the second mask layer is a silicon dioxide layer. 4. A pattern sheet comprising a first mask layer, a second mask layer, a third mask layer, a dielectric layer, and a substrate sequentially arranged in stacks from top to bottom, wherein: the first mask layer is a photoresist layer and includes a first hole penetrating the first mask layer along a thickness direction of the first mask layer and satisfies: d 1 ′ × S 5 ′ > d 2 ′ , and d 2 ′ × S 6 ′ ⩾ d 3 ′ , and d 3 ′ ⩾ ( d 1 ′ - d 4 ′ / S 3 ′ ) ×
Assignees
Inventors
Classifications
Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title
comprising use of blind vias during the manufacture · CPC title
the interconnections being through-semiconductor vias · CPC title
Shapes or dispositions of interconnections · CPC title
for connecting multiple chips together · CPC title
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Frequently asked questions
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- What does patent US12106970B2 cover?
- The present disclosure discloses a pattern sheet, a semiconductor intermediate product, and a hole etching method. The pattern sheet includes a substrate, a dielectric layer, and a mask structure. The mask structure includes a multi-layer mask layer. An uppermost mask layer is a photoresist layer. A thickness of each layer of the mask layer and etching selectivity ratios between the layers belo…
- Who is the assignee on this patent?
- Beijing Naura Microelectronics Equipment Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10P50/692. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Oct 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).