Display panel and manufacturing method thereof

US12105381B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12105381-B2
Application numberUS-202117440729-A
CountryUS
Kind codeB2
Filing dateJul 27, 2021
Priority dateJul 16, 2021
Publication dateOct 1, 2024
Grant dateOct 1, 2024

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  1. Title

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  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present application discloses a display panel and a manufacturing method thereof. The display panel has a display area and a non-display area arranged around the display area. The display panel includes a first substrate, a second substrate, and a first seal, and a second seal disposed between the first substrate and the second substrate. The first seal is doped with conductors. In the present application, the first seal doped with the conductors is provided, and signal traces in the first substrate and a common electrode in the second substrate are conducted by the conductors.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel, having a display area and a non-display area arranged around the display area, wherein the display panel comprises: a first substrate comprising a signal trace, wherein the signal trace is located in the non-display area; a second substrate disposed opposite to the first substrate, and comprising a common electrode; a first seal covering a part of the signal trace and doped with conductors, wherein the conductors conduct the signal trace to the common electrode; and a second seal disposed between the first substrate and the second substrate and located in the non-display area, wherein the second seal is a closed structure surrounding the display area, or the second seal and the first seal at least constitute the closed structure surrounding the display area; wherein the display area has a first side and a second side opposite to each other, and a third side and a fourth side opposite to each other, and the first side, the third side, the second side, and the fourth side are connected in sequence; wherein the signal trace comprises a signal output line and at least one signal input line, the signal output line is connected to the signal input line; the signal output line is arranged around the second side, the third side, and the fourth side, and the signal input line is arranged around a part of the first side; and wherein the first seal comprises a first sub-seal part, and the first sub-seal part covers the signal output line. 2. The display panel according to claim 1 , wherein the first substrate further comprises an insulating layer, the insulating layer covers the signal trace, the insulating layer is provided with an opening, and an orthographic projection of the opening on the first substrate coincides with an orthographic projection of the signal output line on the first substrate, and the conductors are connected to the signal trace through the opening. 3. The display panel according to claim 1 , wherein the display panel further comprises at least one trace portion, the trace portion is located in the non-display area and is arranged adjacent to the first side, and the signal input line crosses the at least one trace portion; and wherein the first seal further comprises at least one second sub-seal part, the second sub-seal part covers a part of the signal input line and is offset from the trace portion. 4. The display panel according to claim 3 , wherein the second seal comprises a main seal, the main seal is the closed structure surrounding the display area, and the main seal is disposed between the first seal and the display area. 5. The display panel according to claim 4 , wherein the second seal further comprises a connecting seal, and the connecting seal is disposed adjacent to the first side; and wherein the connecting seal comprises a first part, and the first part connects the first sub-seal part and the second sub-seal part. 6. The display panel according to claim 5 , wherein the connecting seal further comprises a second part, and the second part is connected to an adjacent one of the first sub-seal part. 7. The display panel according to claim 6 , wherein the connecting seal and the second sub-seal part are located on a same horizontal line. 8. The display panel according to claim 4 , wherein the second seal further comprises a third sub-seal part, and the third sub-seal part is connected between the main seal and the first sub-seal part and disposed adjacent to the first side. 9. The display panel according to claim 8 , wherein the third sub-seal part is arranged as two third sub-seal parts, and one of the third sub-seal parts connects the main seal to the first sub-seal part located at the third side, and another one of the third sub-seal parts connects the main seal to the first sub-seal part located at the fourth side. 10. The display panel according to claim 3 , wherein the second seal is the closed structure surrounding the display area, and the second seal is located at a peripheral side of the first seal away from the display area. 11. The display panel according to claim 3 , wherein the second seal is disposed between the second sub-seal part and the first side, and the second seal extends in a direction parallel to the first side, opposite ends of the second seal are respectively connected to the second sub-seal part. 12. The display panel according to claim 11 , wherein opposite ends of the second seal respectively cross and overlap the first sub-seal part. 13. The display panel according to claim 3 , wherein the second seal is disposed adjacent to the first side; and wherein the second seal comprises a first part, and the first part connects the first sub-seal part to the second sub-seal part. 14. The display panel according to claim 13 , wherein the second seal further comprises a second part, and the second seal connects an adjacent one of the first sub-seal part. 15. The display panel according to claim 1 , wherein the first substrate further comprises an insulating layer and a transparent conductive layer, the insulating layer covers the signal trace, the insulating layer is provided with an opening, the opening exposes the signal trace, the transparent conductive layer is located in the opening, and the conductors are connected to the signal trace through the transparent conductive layer. 16. The display panel according to claim 15 , wherein an orthographic projection of the opening on the first substrate coincides with an orthographic projection of the first seal on the first substrate. 17. The display panel according to claim 1 , wherein supports are further provided in the first seal, and a mass ratio of the supports to the conductors is 1:1.5 to 1:4. 18. The display panel according to claim 17 , wherein the supports are further provided in the second seal. 19. The display panel according to claim 1 , wherein supports are provided in the second seal.

Assignees

Inventors

Classifications

  • conductive · CPC title

  • Spacer materials; Spacer properties · CPC title

  • Conductors connecting electrodes to cell terminals · CPC title

  • G02F1/1339Primary

    Gaskets; Spacers; Sealing of cells · CPC title

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Frequently asked questions

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What does patent US12105381B2 cover?
The present application discloses a display panel and a manufacturing method thereof. The display panel has a display area and a non-display area arranged around the display area. The display panel includes a first substrate, a second substrate, and a first seal, and a second seal disposed between the first substrate and the second substrate. The first seal is doped with conductors. In the pres…
Who is the assignee on this patent?
Huizhou China Star Optoelectronics Display Co Ltd, Tcl China Star Optoelectronics Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/1339. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).