Driver circuit

Patent metadata

Field	Value
Publication number	US-12101084-B2
Application number	US-201917782912-A
Country	US
Kind code	B2
Filing date	Dec 12, 2019
Priority date	Dec 12, 2019
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A driver circuit includes a differential pair of transistors that amplify differential input signals and output the amplified differential input signals from signal output terminals, a current source that supplies a constant current to the differential pair of transistors, a switch that stops the current supply from the current source to the differential pair of transistors during a shutdown mode period, capacitors each having one end connected to the ground, a switch that connects the capacitor to the signal output terminal during the shutdown mode period and disconnects the capacitor from the signal output terminal during an amplification mode period, and a switch that connects the capacitor to the signal output terminal during the shutdown mode period and disconnects the capacitor from the signal output terminal during the amplification mode period.

First claim

The invention claimed is:

1. A driver circuit comprising:
a differential pair of transistors configured to amplify differential input signals and output the amplified differential input signals from a pair of signal output terminals;
a current source configured to supply a constant current to the differential pair of transistors;
a first switch configured to stop the current supply from the current source to the differential pair of transistors during a shutdown mode period, a shutdown signal being a control input to the first switch;
a first capacitor and a second capacitor each having one end connected to the ground;
a second switch configured to connect another end of the first capacitor to the signal output terminal on a positive phase side during the shutdown mode period and disconnect the first capacitor from the signal output terminal on the positive phase side during an amplification mode period, an inversion of the shutdown signal being a control input to the second switch; and
a third switch configured to connect another end of the second capacitor to the signal output terminal on a negative phase side during the shutdown mode period and disconnect the second capacitor from the signal output terminal on the negative phase side during the amplification mode period, the inversion of the shutdown signal being a control input to the second switch.

2. The driver circuit according to claim 1 , further comprising:
a first control circuit configured to perform control such that the first switch is ON and the second and third switches are OFF during the amplification mode period and that the first switch is OFF and the second and third switches are ON during the shutdown mode period.

3. The driver circuit according to claim 2 , further comprising:
a variable resistor made of a MOS transistor inserted between the pair of signal output terminals.

4. The driver circuit according to claim 3 , further comprising:
a second control circuit configured to set a control voltage to be applied to a gate terminal of the MOS transistor in response to a gain control signal for setting a gain of the driver circuit to an intended value during the amplification mode period and set the control voltage higher than a power source voltage of the driver circuit during the shutdown mode period.

5. A driver circuit comprising:
a differential pair of transistors configured to amplify differential input signals and output the amplified differential input signals from a pair of signal output terminals;
a current source configured to supply a constant current to the differential pair of transistors;
a first switch configured to stop the current supply from the current source to the differential pair of transistors during a shutdown mode period;
a first capacitor and a second capacitor each having one end connected to the ground;
a second switch configured to connect another end of the first capacitor to the signal output terminal on a positive phase side during the shutdown mode period and disconnect the first capacitor from the signal output terminal on the positive phase side during an amplification mode period;
a third switch configured to connect another end of the second capacitor to the signal output terminal on a negative phase side during the shutdown mode period and disconnect the second capacitor from the signal output terminal on the negative phase side during the amplification mode period;
a variable resistor made of a MOS transistor inserted between the pair of signal output terminals;
a first control circuit configured to set a control voltage to be applied to a gate terminal of the MOS transistor in response to a gain control signal for setting a gain of the driver circuit to an intended value during the amplification mode period and set the control voltage higher than a power source voltage of the driver circuit during the shutdown mode period; and
a second control circuit configured to perform control such that the ON/OFF states of the second and third switches are reverse to the ON/OFF state of the first switch.

6. The driver circuit according to claim 5 , wherein the second control circuit is further configured to perform control such that the first switch is ON and the second and third switches are ON during the amplification mode period and that the first switch is OFF and the second and third switches are ON during the shutdown mode period.

7. The driver circuit according to claim 5 , wherein
the MOS transistor includes:
a first MOS transistor having a source terminal connected to the signal output terminal on the positive phase side; and
a second MOS transistor having a drain terminal connected to a drain terminal of the first MOS transistor and having a source terminal connected to the signal output terminal on the negative phase side, and
the first control circuit uses, as the control voltage during the shutdown mode period, a voltage obtained by adding the power source voltage of the driver circuit to a maximum voltage that can be applied between a gate terminal and the source terminal of each of the first and second MOS transistors.

8. A driver circuit comprising:
a differential pair of transistors configured to amplify differential input signals and output the amplified differential input signals from a pair of signal output terminals;
a current source configured to supply a constant current to the differential pair of transistors;
a first switch configured to couple the current source to the differential pair of transistors during an amplification mode period and to decouple the current source from the differential pair of transistors during a shutdown mode period;
a first capacitor and a second capacitor each having one end connected to a ground terminal;
a second switch configured to connect another end of the first capacitor to the signal output terminal on a positive phase side during the shutdown mode period and disconnect the first capacitor from the signal output terminal on the positive phase side during the amplification mode period;
a third switch configured to connect another end of the second capacitor to the signal output terminal on a negative phase side during the shutdown mode period and disconnect the second capacitor from the signal output terminal on the negative phase side during the amplification mode period;
a variable resistor comprising a MOS transistor coupled between the pair of signal output terminals; and
a control circuit configured to:
control the first, second, and third switches such that the first switch couples the current source to the differential pair during the amplification mode period while the second and third switches decouple the capacitors from the output terminals, and such that the first switch decouples the current source from the differential pair during the shutdown mode period while the second and third switches couple the capacitors to the output terminals; and
set a control voltage applied to a gate terminal of the MOS transistor based on a gain control signal to set a gain of the driver circuit during the amplification mode period, and to set the control voltage higher than a power supply voltage of the driver circuit during the shutdown mode period.

9. The driver circuit of claim 8 , wherein the control circuit is further configured to:
control the first, second and third switches such that the ON/OFF states of the second and third switches are reverse to the ON/OFF state of the first switch.

10. The driver circuit of claim 8 , further comprising:
a first resistor coupled between a power supply voltage and the signal output terminal on the positive phase side; and
a second resistor coupled between the power supply voltag

Assignees

• Nippon Telegraph & Telephone

Inventors

• Jo Teruo
• Nagatani Munehiko
• Nosaka Hideyuki

Classifications

• H04L25/02

  Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} · CPC title

• H03K19/0175

  Coupling arrangements; Interface arrangements (interface arrangements for digital computers G06F3/00, G06F13/00) · CPC title

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03F3/45188 Primary

  Non-folded cascode stages · CPC title