Reliable semiconductor packages

Patent metadata

Field	Value
Publication number	US-12100719-B2
Application number	US-202117352348-A
Country	US
Kind code	B2
Filing date	Jun 20, 2021
Priority date	Jun 22, 2020
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A semiconductor package and method for forming thereof are disclosed. The package includes a package substrate having a die region with a die attached thereto. An encapsulant is disposed to cover encapsulation region of the package substrate. A protective cover is disposed over the die and attached to the encapsulant by a cover adhesive. The protective cover is supported by a lower portion of step shaped inner encapsulant sidewalls.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate having top and bottom major package substrate surfaces, wherein the top major package substrate surface includes a die region and an encapsulation region surrounding the die region with a gap region between the die attach region and the encapsulation region, wherein the package substrate includes
a core package substrate with alternating metal and dielectric core package substrate layers, wherein a top package substrate layer comprises a top metal package substrate layer,
a package substrate layer encasing top, bottom and side core package surfaces,
package bond pads on the top major package surface,
package contact pads on the bottom major package surface, wherein the package bond pads are connected to the package contact pads via metal traces and via contacts of the core package substrate;

a die disposed on the die region, wherein the die includes first and second major die surfaces, the second major die surface is attached to the die region, wherein die bond pads of the die are electrically connected to the package bond pads;
at least one encapsulation interlock in the encapsulation region, the encapsulant interlock penetrates through the package substrate layer encasing the core package substrate to at least the top core substrate surface;
a cavity structure, the cavity structure includes top and bottom surfaces, outer structure sidewalls defining external sidewalls of the package and inner structure sidewalls defining a cavity of the cavity structure, wherein the bottom surface of the cavity structure is disposed on the encapsulation region of the package substrate, the cavity structure encases the at least one encapsulation interlock, wherein the encapsulation interlock prevents delamination of the cavity structure from the package substrate; and
a protective cover disposed on the cavity structure, wherein the protective cover and the cavity structure form a hermetic cavity with a predetermined cavity height over the die.

2. The semiconductor package in claim 1 , wherein the encapsulant interlock comprises a recess structure within the encapsulation region which extends through the package substrate layer to expose the core package substrate, wherein the cavity structure fills the recess structure.

3. The semiconductor package in claim 2 , wherein the recess structure is lined with an adhesive layer.

4. The semiconductor package in claim 2 , wherein the recess structure comprises a processed inner recess surface, wherein the processed inner recess surface comprises a roughened inner recess surface.

5. The semiconductor package in claim 1 , wherein the encapsulation interlock comprises a protruded structure, wherein the protruded structure extends from the core package substrate and above the package substrate layer, a portion of the protruded structure above the package substrate layer is encased by the cavity structure.

6. The semiconductor package in claim 5 , wherein the protruded structure comprises an anchor-shaped structure to anchor the cavity structure to the package substrate.

7. The semiconductor package in claim 5 , wherein the portion of the protruded structure above the package substrate layer comprises a solder structure to anchor the cavity structure to the package substrate.

8. The semiconductor package in claim 1 , wherein the encapsulation interlock comprises a recess structure and a protruded structure disposed within the recess structure, the cavity structure fills the recess structure and encases the protruded structure.

9. The semiconductor package in claim 8 , wherein the protruded structure comprises an anchor-shaped structure to anchor the cavity structure to the package substrate.

10. The semiconductor package in claim 1 , wherein the at least one encapsulation interlock comprises a plurality of encapsulant interlocks, wherein the encapsulation interlocks comprise recess structures, protruded structures, wherein the protruded structures are disposed within the recessed structures, or a combination thereof.

11. The semiconductor package of claim 10 , wherein the encapsulation interlocks comprise continuous concentric encapsulation interlocks in the encapsulation region.

12. The semiconductor package of claim 1 , wherein the cavity structure comprises a molded compound.

13. The semiconductor package of claim 1 , wherein the cavity structure comprises a cured adhesive.

14. A semiconductor package comprising:
a package substrate having top and bottom major package substrate surfaces, wherein the top major package substrate surface includes a die region and an encapsulation region surrounding the die region with a gap region between the die attach region and the encapsulation region, wherein the package substrate includes
a core package substrate, and
a package substrate layer encasing top, bottom and side core package surfaces;

encapsulation interlocks in the encapsulation region, the encapsulation interlocks penetrate through the package substrate layer encasing the core package substrate to the core package substrate;
a cavity structure, the cavity structure includes top and bottom cavity structure surfaces, outer cavity structure sidewalls defining external sidewalls of the package and inner cavity structure sidewalls defining a cavity of the cavity structure, wherein the bottom cavity structure surface is disposed on the encapsulation region, the cavity structure encases the encapsulation interlocks, wherein the encapsulation interlocks prevent delamination of the cavity structure from the package substrate; and
wherein the cavity structure is configured to accommodate a protective cover to produce a hermetic cavity when a die is attached to the die attach region.

15. The semiconductor package in claim 14 , wherein the encapsulant interlocks comprise recess structures within the encapsulation region which extends through the package substrate layer to expose the core package substrate, wherein the cavity structure fills the recess structures.

16. The semiconductor package in claim 15 , wherein the recess structures include a processed inner recess surface, the processed inner surface comprises:
an adhesive layer lining the processed inner recess surface;
a roughened surface; or
a combination thereof.

17. The semiconductor package in claim 15 , wherein the encapsulation interlocks comprise protruded structures, wherein the protruded structures extend from the core package substrate and above the package substrate layer, a portion of the protruded encapsulation interlock above the package substrate layer is encased by the cavity structure.

18. The semiconductor package in claim 17 , wherein the protruded structures comprise:
anchor-shaped structures to anchor the cavity structure to the package substrate;
solder structures; or
a combination thereof.

19. The semiconductor package of claim 14 , wherein the encapsulant interlocks comprise:
recess structures within the encapsulation region which extends through the package substrate layer to expose the core package substrate, wherein the cavity structure fills the recess structures;
protruded structures, wherein the protruded structures extend from the core package substrate and above the package substrate layer, a portion of the protruded encapsulation interlock above the package substrate layer is encased by the cavity structure;
protruded structures disposed within recessed structures; or
a combination thereof.

20. The semiconductor

Assignees

• Utac Headquarters Pte Ltd

Inventors

• Punzalan Jeffrey
• Shim Il Kwon

Classifications

• H10F39/011

  Manufacture or treatment of image sensors covered by group H10F39/12 · CPC title

• H10F39/804 Primary

  Containers or encapsulations · CPC title

• H01L27/14683

  Electricity · mapped topic

• H01L27/14618 Primary

  Electricity · mapped topic