Apparatus, memory controller, memory device, memory system, and method for clock switching and low power consumption

Patent metadata

Field	Value
Publication number	US-12100475-B2
Application number	US-202318496693-A
Country	US
Kind code	B2
Filing date	Oct 27, 2023
Priority date	Dec 17, 2020
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

In an apparatus, a memory controller, a memory device, and a method for switching frequencies of clock signals to reduce power consumption, when the memory device performs an internal operation according to a command of the memory controller, a frequency of a clock signal of the memory controller is changed. The memory controller switches the frequency of the clock signal to a low frequency according to assertion of a status signal that indicates a busy operation status of the memory device according to the command, and switches the frequency of the clock signal to a high frequency according to de-assertion of the status signal that indicates a ready operation status of the memory device.

First claim

What is claimed is:

1. A memory device comprising:
a plurality of signal pins connected to signal lines through which signals are respectively carried; and
a control logic circuit configured to control a first operation relating to a first command in response to the first command received through first signal pins from among the plurality of signal pins,
wherein, during the first operation, the memory device is configured to transmit a status signal indicating an operation status of the memory device through a second signal pin from among the plurality of signal pins, and transmit and receive a clock signal that is toggled at a changed frequency relating to the status signal through a third signal pin from among the plurality of signal pins,
when the first command is a read command, the memory device is further configured to receive the clock signal that is toggled at a low frequency while reading data stored in memory cells of the memory device, and transmit the clock signal that is toggled at a high frequency while transmitting the data read from the memory cells through the first signal pins.

2. The memory device of claim 1 , wherein the memory device is further configured to receive a status check signal for checking a status of the memory device through some of the plurality of signal pins, and transmit a status output signal corresponding to the status check signal as the status signal.

3. The memory device of claim 1 , wherein the control logic circuit is further configured to control a second operation relating to a second command in response to the second command received through the first signal pins, and
during the second operation performed when the second command is a write command, the memory device is further configured to receive the clock signal that is toggled at a high frequency while the memory device receives write data, and receive the clock signal that is toggled at a low frequency while programming the write data to memory cells of the memory device.

4. The memory device of claim 3 , wherein the clock signal does not toggle while the write data is programmed to the memory cells of the memory device.

5. The memory device of claim 1 , wherein the status signal is associated with a ready-busy output signal.

6. The memory device of claim 1 , wherein the clock signal is associated with a data strobe signal.

7. A memory system comprising:
a memory device including a plurality of memory cells; and
a memory controller configured to transmit a first command and a clock signal to the memory device to control the memory device,
wherein the memory controller is configured to switch a frequency of the clock signal to a first frequency according to assertion of a status signal provided from the memory device that indicates an operation status of the memory device according to the command, and switch the frequency of the clock signal to a second frequency different from the first frequency according to de-assertion of the status signal,
when the first command is a read command, the memory device is configured to receive the clock signal having the first frequency that is toggled at a low frequency while reading data stored in memory cells of the memory device, and transmit the clock signal having the second frequency that is toggled at a high frequency while transmitting the read data to the memory controller.

8. The memory system of claim 7 , wherein the memory system is set to a low-power operation mode associated with the clock signal having the first frequency, and is set to a high-power operation mode associated with the clock signal having the second frequency, the first frequency is a low frequency, and the second frequency is a high frequency.

9. The memory system of claim 7 , wherein the memory controller is further configured to transmit a second command to the memory device,
when the second command is a write command, the memory device receives the clock signal having the second frequency that is toggled to a high frequency while the memory device receives write data, and receives the clock signal having the first frequency that is toggled to a low frequency while programming the write data to memory cells.

10. The memory system of claim 9 , wherein the clock signal does not toggle while the write data is programmed to the memory cells of the memory device.

11. The memory system of claim 7 , wherein the status signal is associated with a ready-busy output signal.

12. The memory system of claim 7 , wherein the status signal is associated with a status output signal that is output by the memory device in response to a status check signal for checking the operation status of the memory device.

13. The memory system of claim 7 , wherein the clock signal is associated with a data strobe signal.

14. The memory system of claim 7 , wherein the clock signal is switched by the memory controller to not toggle according to assertion of the status signal.

15. A method of providing a clock signal, the method comprising:
determining, by a memory controller, a first command for an operation condition of a memory device;
performing, by the memory device, a first operation in response to the first command, wherein the first operation includes a read operation or a write operation of the memory device, and a frequency of the clock signal is set to be relatively higher when the memory device performs the read operation than when the memory device performs the write operation;
asserting, by the memory device, a status signal indicating a status of the first operation;
switching, by the memory controller, a frequency of the clock signal to a first frequency in response to the assertion of the status signal;
de-asserting, by the memory device, the status signal; and
switching, by the memory controller, the frequency of the clock signal to a second frequency different from the first frequency according to the de-assertion of the status signal.

16. The method of claim 15 , wherein the first operation comprises a low-power operation mode associated with the clock signal having the first frequency, and a high-power operation mode associated with the clock signal having the second frequency, the first frequency being a low frequency, and the second frequency being a high frequency.

17. The method of claim 15 , further comprising:
receiving, at the memory device, the clock signal having the first frequency that is toggled at a low frequency while reading data stored in memory cells of the memory device when the first command is a read command; and
transmitting, by the memory device, the clock signal having the second frequency that is toggled at a high frequency while the memory device transmits the read data to the memory controller.

18. The method of claim 15 , further comprising:
receiving, at the memory device, the clock signal having the second frequency that is toggled at a high frequency while the memory device receives write data when the first command is a write command; and
receiving, at the memory device, the clock signal having the first frequency that is toggled at a low frequency while programming the write data to memory cells of the memory device.

19. The method of claim 15 , wherein the status signal is associated with a status output signal output in response to a status check signal for checking a status of the memory device.

20. The method of claim 15 , wherein the switching of the frequency of the clock signal to the first frequency in response to the assertion of the status signal compr

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyungjin
• Park Jungsik
• Shin Soongmann

Classifications

• G11C7/1063 Primary

  Control signal output circuits, e.g. status or busy flags, feedback command signals · CPC title

• G11C7/109

  Control signal input circuits · CPC title

• G11C8/18

  Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title