Method and apparatus for analog floating gate memory cell

Patent metadata

Field	Value
Publication number	US-12100453-B2
Application number	US-202117498686-A
Country	US
Kind code	B2
Filing date	Oct 11, 2021
Priority date	Oct 11, 2021
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A floating-node memory device includes a metal-oxide-semiconductor (MOS) transistor including a first polysilicon gate, a source region, and a drain region in a first well region, a tunneling device including a second polysilicon gate in a second well region, and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer. The floating-node device includes a floating-node comprising the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor coupled together, a control node at the bottom plate of the MIM capacitor, an erase node in the second well region, a source node at the source region of the MOS transistor, and a drain node at the drain region of the MOS transistor.

First claim

What is claimed is:

1. A non-volatile memory device, comprising:
a floating-node memory cell, including:
a P-type metal-oxide-semiconductor (PMOS) transistor having a first polysilicon gate;
a tunneling device having a second polysilicon gate; and
a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer,
wherein the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor are coupled together to form a floating-node;

a high-voltage input node for coupling to a programmable high-voltage source;
a high-voltage switch circuit coupled to the high-voltage input node for providing a voltage signal for performing:
hot-electron programming of the first polysilicon gate in the PMOS transistor; and
tunneling erase of the second polysilicon gate in the tunneling device; and

wherein the high-voltage switch circuit comprises:
PMOS transistors M1, M2, M3, and M4;
NMOS transistors M5, M6, M7, M8, and M9;
wherein:
M1, M3, M5, M7, and M9 are coupled in series between the high-voltage input node and a ground node, a drain node of M9 coupled to a source node of M9;
M2, M4, M6, and M8 are coupled in series between the high-voltage input node and the ground node, a node between M4 and M6 providing a high-voltage signal to the memory device;
M1 and M2 are coupled to form a current mirror;
a gate node of M3 is coupled to a gate node of M4;
a gate node of M3 and gate node M4 is coupled to a power supply;
a gate node of M5 and a gate node of M6 are coupled to a power supply voltage;
a gate node of M7 and a gate node of M8 are coupled to a control signal and a complement of the control signal, respectively.

2. The memory device of claim 1 , wherein the memory device is disposed in an integrated circuit (IC), and the programmable high-voltage source is disposed external to the IC.

3. The memory device of claim 1 , wherein the power supply voltage is lower than the voltage at the high-voltage input node.

4. The memory device of claim 1 , wherein the first polysilicon gate and the second polysilicon gate are connected by a second layer metal interconnect.

5. The memory device of claim 1 , wherein the first polysilicon gate and the second polysilicon gate are connected by a first layer metal interconnect.

6. The memory device of claim 1 , wherein the MIM capacitor is characterized by an area that is 50% to 90% of an area of the floating-node memory device.

7. A non-volatile memory device, comprising:
a floating-node memory cell disposed in an integrated circuit (IC), including:
a floating-node;
a control node;
an erase node;
a source node; and
a drain node;

a high-voltage input node for coupling to an external programmable high-voltage source external to the IC; and
a high-voltage switch circuit coupled to the high-voltage input node for providing a voltage signal for performing:
hot-electron programming of charges to the floating node; and
tunneling erase of charges from the floating node;

wherein the high-voltage switch circuit comprises:
PMOS transistors M1, M2, M3, and M4;
NMOS transistors M5, M6, M7, M8, and M9;

wherein:
M1, M3, M5, M7, and M9 are coupled in series between the high-voltage input node and a ground node, a drain node of M9 coupled to a source node of M9;
M2, M4, M6, and M8 are coupled in series between the high-voltage input node and the ground node, a node between M4 and M6 providing an high-voltage signal to the memory device;
M1 and M2 are coupled to form a current mirror;
a gate node of M3 is coupled to a gate node of M4;
a gate node of M3 and gate node M4 is coupled to a power supply;
a gate node of M5 and a gate node of M6 are coupled to a power supply voltage; and
a gate node of M7 and a gate node of M8 are coupled to a control signal and a complement of the control signal, respectively.

8. The memory device of claim 7 , wherein the power supply voltage is lower than the voltage at the high-voltage input node.

9. The memory device of claim 7 , wherein the floating-node memory cell, includes:
a P-type metal-oxide-semiconductor (PMOS) transistor having a first polysilicon gate;
a tunneling device having a second polysilicon gate; and
a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer,
wherein the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor are coupled together to form the floating-node.

10. The memory device of claim 9 , wherein the floating-node device comprises:
a control node at the bottom plate of the MIM capacitor;
an erase node at a well region of the tunneling device;
a source node at a source region of the PMOS transistor; and
a drain node at a drain region of the PMOS transistor.

11. The memory device of claim 9 , wherein the first polysilicon gate and the second polysilicon gate are connected in the second layer metal interconnect.

12. The memory device of claim 9 , wherein the first polysilicon gate and the second polysilicon gate are connected in the first layer metal interconnect.

13. The memory device of claim 9 , wherein the MIM capacitor is disposed over the PMOS transistor and the tunneling device.

Assignees

• Nuvoton Technology Corp

Inventors

• Sandhu Bal S
• Voorde Paul Vande
• Wu chang-xian

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10D30/685

  from the channel · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10B41/30

  characterised by the memory core region · CPC title

• G11C27/005

  with non-volatile charge storage, e.g. on floating gate or MNOS · CPC title