Verify failbit count circuit, memory device, memory system and method

Patent metadata

Field	Value
Publication number	US-12099729-B2
Application number	US-202218090384-A
Country	US
Kind code	B2
Filing date	Dec 28, 2022
Priority date	Mar 15, 2021
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

The present disclosure relates to a verify failbit count circuit, comprising: a highest bit counter configured to compare a verify standard signal with a verify failbit signal to generate a first comparison result, and output a first enable signal based on the first comparison result; a lowest bit counter configured to, in response to a first enable signal indicating to enable the lowest bit counter, compare the verify failbit signal with a first reference signal to generate a second comparison result, and output a second enable signal based on the second comparison result; and a first intermediate bit counter configured to, in response a the second enable signal indicating to enable the first intermediate bit counter, compare the verify failbit signal with a second reference signal to generate a third comparison result.

First claim

What is claimed is:

1. A circuit for verifying failbit count in a semiconductor memory device, comprising:
a highest bit counter configured to:
receive a verify standard signal and a verify failbit signal, wherein the verify standard signal is a highest bit standard signal of the circuit;
compare the verify standard signal with the verify failbit signal to generate a first comparison result, and
output a first enable signal based on the first comparison result;

a lowest bit counter being connected to the highest bit counter and configured to:
receive the first enable signal, the verify failbit signal, and a first reference signal, wherein the first reference signal is a lowest bit standard signal of the circuit,
in response to the first enable signal indicating to enable the lowest bit counter, compare the verify failbit signal with the first reference signal to generate a second comparison result, and
output a second enable signal based on the second comparison result; and

a first intermediate bit counter connected to the lowest bit counter and configured to:
receive the second enable signal, the verify failbit signal, and a second reference signal higher than the first reference signal and lower than the verify standard signal, and
in response to the second enable signal indicating to enable the first intermediate bit counter, compare the verify failbit signal with the second reference signal to generate a third comparison result.

2. The circuit of claim 1 , further comprising:
a plurality of intermediate bit counters that are connected sequentially based on their respective reference signals from low to high, wherein:
a reference signal of lower intermediate bit counter is lower than a reference signal of a higher intermediate bit counter,
a switch between an enabled status and a disabled status of each intermediate bit counter is controlled by its adjacent lower intermediate bit counter.

3. The circuit of claim 2 , wherein the plurality of intermediate bit counters comprises:
a second intermediate bit counter arranged adjacent to the first intermediate bit counter, and configured to:
receive a third enable signal output by the first intermediate bit counter based on the third comparison result,
receive the verify failbit signal, and a third reference signal higher than the second reference signal and lower than or equal to the verify standard signal, and
in response to the third enable signal indicating to enable the second intermediate bit counter, compare the verify failbit signal with the third reference signal to generate a fourth comparison result.

4. The circuit of claim 3 , wherein the highest bit counter comprises:
a first comparator configured to:
receive the verify standard signal and the verify failbit signal,
compare the verify standard signal with the verify failbit signal to generate the first comparison result, and
output the first comparison result; and

a first inverter connected to the first comparator and configured to:
receive the first comparison result, and
output the first enable signal based on the first comparison result, wherein the first enable signal is an inverse signal of the first comparison result.

5. The circuit of claim 4 , wherein the lowest bit counter comprises:
a first control circuit connected to the highest bit counter and configured to:
receive the first enable signal, and
control a switch between an enabled status and a disabled status of the lowest bit counter based on the first enable signal; and

a second comparator configured to:
receive the verify failbit signal and the first reference signal when the lowest bit counter is in the enabled status, and
compare the verify failbit signal with the first reference signal to generate the second comparison result.

6. The circuit of claim 5 , wherein the second comparator is further configured to:
output the second enable signal based on the second comparison result, wherein the second enable signal is in phase with the second comparison result.

7. The circuit of claim 5 , wherein the first control circuit comprises a P-type transistor T 1 , a P-type transistor T 2 , and an N-type transistor T 3 , wherein:
a drain of the P-type transistor T 1 is connected to a source of the P-type transistor T 2 ;
a drain of the P-type transistor T 2 is connected to a drain of the N-type transistor T 3 ;
a base of the P-type transistor T 1 is connected to an output terminal of the first inverter;
a base and the drain of the P-type transistor T 2 are connected to the verify failbit signal;
a base of the N-type transistor T 3 is connected to the first reference signal; and
the P-type transistor T 1 is turned on or turned off based on the first enable signal to control the switch between the enabled status and the disabled status of the lowest bit counter.

8. The circuit of claim 7 , wherein the first control circuit further comprises an N-type transistor T 4 and a first NAND gate; wherein:
a drain of the N-type transistor T 4 is connected to a source of the N-type transistor T 3 ;
a base of the N-type transistor T 4 is connected to an output terminal of the first NAND gate; and
the N-type transistor T 4 is turned off when the first NAND gate outputs a low level signal to turn off the lowest bit counter.

9. The circuit of claim 8 , wherein the first NAND gate comprises:
a first input terminal connected to a system voltage VDD; and
a second input terminal connected to the second enable signal.

10. The circuit of claim 9 , wherein each of the plurality of intermediate bit counters has a same structure with the lowest bit counter.

11. The circuit of claim 5 , wherein:
the highest bit counter is further configured to: output a fourth enable signal based on the result of the first comparison; and
the lowest bit counter further includes a first OR gate, two input terminals of the first OR gate are respectively connected to the fourth enable signal and the second enable signal respectively, and an output of the first OR gate is used as the second comparison result output by the lowest bit counter.

12. The circuit of claim 10 , wherein:
the highest bit counter is further configured to output a fourth enable signal based on the result of the first comparison;
the first intermediate bit counter further includes a second OR gate, two input terminals of the second OR gate are respectively connected to the fourth enable signal and the third enable signal, and an output of the second OR gate is used as the third comparison result output by the first intermediate bit counter.

13. The circuit of claim 1 , further comprising:
a code converter configured to convert a thermometer code into a binary code, wherein the first comparison result, the third comparison result, and the second comparison result are inputs of the code converter from high bit to low bit.

14. The circuit of claim 13 , further comprising:
an accumulator configured to accumulate a plurality of binary codes obtained from the code converter.

15. The circuit of claim 1 , further comprising:
a verify standard selector configured to select one from at least two verify standards with different magnitudes as the verify standard signal.

16. A method for verifying failbit count in a semiconductor memory by a circuit, comprising:
selecting one from at least two verify standards with different magnitudes as a verify standard signal for a highest bit;
comparing a verify failbit signal with the verify standard signal to generate a first comparison result;
outputting a first enable sign

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Cao Yi

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title