Secure peripheral component access

Patent metadata

Field	Value
Publication number	US-12099602-B2
Application number	US-202217728619-A
Country	US
Kind code	B2
Filing date	Apr 25, 2022
Priority date	Oct 23, 2019
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A device includes a non-maskable interrupt (NMI) signal path, a processor, and a peripheral component. The peripheral component may comprise secret data, such as a secret key. The processor may perform a preconfigured NMI interrupt service routine (ISR), in response to detecting a preconfigured signal in the NMI signal path. Access to at least a part of the peripheral component may be enabled in response to detecting the preconfigured signal in the NMI signal path. Thus, the processor may be able to access the secret data, for example, when the processor is running the NMI ISR.

First claim

What is claimed is:

1. A device comprising:
a non-maskable interrupt (NMI) signal path;
a non-volatile memory storing a program code;
a processor electrically coupled to the NMI signal path and the non-volatile memory, wherein the processor is configured to:
in response to detecting a preconfigured signal in the NMI signal path, perform a preconfigured NMI interrupt service routine (ISR) by executing in place (XIP), from the non-volatile memory, the program code stored in the non-volatile memory, wherein at least a part of the non-volatile memory that stores the program code is write-protected; and

a peripheral component electrically coupled to the NMI signal path, wherein the peripheral component is configured to:
in response to detecting the preconfigured signal in the NMI signal path, enable an access to at least a part of the peripheral component.

2. The device according to claim 1 , wherein the processor comprises an output electrically coupled to the NMI signal path.

3. The device according to claim 1 , wherein the processor comprises a non-maskable interrupt (NMI) input and the NMI signal path is electrically coupled to the processor via the NMI input.

4. The device according to claim 1 , further comprising:
an interrupt controller comprising an output, wherein the NMI signal path is electrically coupled to the output of the interrupt controller.

5. The device according to claim 4 , wherein the interrupt controller further comprises a first input and the processor further comprises an output, wherein the output of the processor is electrically coupled to the first input of the interrupt controller.

6. The device according to claim 5 , wherein the interrupt controller comprises a second input configured to receive external interrupt signals.

7. The device according to claim 1 , wherein the processor is further configured to:
during the preconfigured NMI ISR, access the peripheral component.

8. The device according to claim 1 , wherein the processor is further configured to:
during the preconfigured NMI ISR, sanitize a state of the processor.

9. The device according to claim 1 , the device further comprising:
a volatile memory,
wherein the processor is further configured to:
after performing the preconfigured NMI ISR, remove data related to the preconfigured NMI ISR from the volatile memory.

10. The device according to claim 1 , wherein the processor is further configured to:
after performing the preconfigured NMI ISR, disable the access to the peripheral component.

11. The device according to claim 1 , wherein the processor is further configured to:
during the preconfigured NMI ISR:
identify a requested operation; and
perform the requested operation using the peripheral component.

12. A method for operating a device comprising a non-maskable interrupt (NMI) signal path, a non-volatile memory, a processor electrically coupled to the NMI signal path and the non-volatile memory, and a peripheral component, the method comprising:
in response to detecting a preconfigured signal in the NMI signal path, performing, by the processor, a preconfigured NMI interrupt service routine (ISR) by executing in place (XIP), from the non-volatile memory, a program code stored in the non-volatile memory, wherein at least a part of the non-volatile memory that stores the program code is write-protected; and
in response to detecting the preconfigured signal in the NMI signal path, enabling, by the peripheral component, an access to at least a part of the peripheral component.

13. A non-transitory computer-readable medium having stored thereon a program code that, when executed by a computing device, causes the computing device to perform the method according to claim 12 .

14. The non-transitory computer-readable medium according to claim 13 , wherein the program code further causes the device to: during the preconfigured NMI ISR, access the peripheral component.

15. The method according to claim 12 , further comprising:
during the preconfigured NMI ISR, accessing, by the processor, the peripheral component.

16. The method according to claim 12 , further comprising:
during the preconfigured NMI ISR, sanitizing, by the processor, a state of the processor.

17. The method according to claim 12 , further comprising:
after performing the preconfigured NMI ISR, disabling, by the processor, the access to the peripheral component.

18. The method according to claim 12 , further comprising:
during the preconfigured NMI ISR,
identifying, by the processor, a requested operation; and
performing, by the processor, the requested operation using the peripheral component.

Assignees

• Huawei Tech Co Ltd

Inventors

• Stoppa Igor
• Ekberg Jan-Erik
• Salko Santeri

Classifications

• G06F21/85 Primary

  interconnection devices, e.g. bus-connected or in-line devices · CPC title

• G06F21/554

  involving event detection and direct action · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F21/556 Primary

  involving covert channels, i.e. data leakage between processes (inhibiting the analysis of circuitry or operation with measures against power attack G06F21/755) · CPC title