Command processing circuitry maintaining a linked list defining entries for one or more command queues and executing synchronization commands at the queue head of the one or more command queues in list order based on completion criteria of the synchronization command at the head of a given command queue

Patent metadata

Field	Value
Publication number	US-12099456-B2
Application number	US-202318098360-A
Country	US
Kind code	B2
Filing date	Jan 18, 2023
Priority date	Jan 18, 2023
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

Circuitry comprises a memory to store data defining a set of one or more command queues each associated with a respective memory address space, each command queue defining successive commands for execution from a queue head to a queue tail, the commands being selected from a set of commands comprising synchronization commands and one or more other commands defining memory management operations for a given memory address space, in which completion of a synchronization command is dependent upon one or more completion criteria indicating that all commands from any of the command queues which are earlier than the synchronization command in an execution order have completed; and command processing circuitry to execute the commands; in which the command processing circuitry is configured to maintain a linked list of entries having a list order, each entry defining a respective one of the command queues, in which the command processing circuitry is configured to execute commands at the head of command queues, the command queues being defined by prevailing entries of the linked list of entries in the list order; and in which, for a current occupancy of the linked list at a given stage, the given stage being a given stage of executing commands from command queues defined by entries of the linked list, the command processing circuitry is configured to execute a synchronization command first in the list order and to detect, within that current occupancy of the linked list at the given stage, any further synchronization commands at the head of command queues which are defined by entries of the linked list later in the list order, the command processing circuitry applying, for any such further synchronization commands, the completion criteria of the synchronization command at the head of a given command queue, the given command queue being defined by an entry of the linked list earliest in the list order so as to treat any such further synchronization commands as having been completed.

First claim

The invention claimed is:

1. Circuitry comprising:
a memory to store data defining a set of one or more command queues each associated with a respective memory address space, each command queue defining successive commands for execution from a queue head to a queue tail, the commands being selected from a set of commands comprising synchronization commands and one or more other commands defining memory management operations for a given memory address space, in which completion of a synchronization command is dependent upon one or more completion criteria indicating that all commands from any of the one or more command queues which are earlier than the synchronization command in an execution order have completed; and
command processing circuitry to execute the commands;
in which the command processing circuitry is configured to maintain a linked list of entries having a list order, each entry defining a respective one of the one or more command queues, in which the command processing circuitry is configured to execute commands at the queue head of the one or more command queues, the one or more command queues being defined by prevailing entries of the linked list of entries in the list order;
and in which, for a current occupancy of the linked list at a given stage of executing commands from the one or more command queues defined by entries of the linked list, the command processing circuitry is configured to execute a first synchronization command earliest in the list order and to detect, within that current occupancy of the linked list at the given stage, any further synchronization commands at the queue head of the one or more command queues which are defined by entries of the linked list later in the list order, the command processing circuitry applying, for any such further synchronization commands, the completion criteria of the synchronization command at the head of a given command queue, the given command queue being defined by an entry of the linked list earliest in the list order so as to treat the further synchronization commands as having been completed.

2. The circuitry of claim 1 , in which the given stage comprises execution of a first command corresponding to a first entry of the linked list.

3. The circuitry of claim 1 , in which the given stage comprises execution of a synchronization command.

4. The circuitry of claim 1 , in which each respective command queue is associated with a command source to provide commands to that respective command queue.

5. The circuitry of claim 4 , in which the command source comprises software executed by one or more processing elements.

6. The circuitry of claim 5 , in which, in response to completion of the synchronization command, the command processing circuitry is configured to issue one or more interrupts to the one or more processing elements which executed the software to provide the synchronization command.

7. The circuitry of claim 6 , in which the one or more processing elements are configured to execute software at a security level selected from two or more security levels.

8. The circuitry of claim 7 , in which each of the command queues are associated with the two or more security levels so as to provide, for a given command source, a respective command queue for each security level.

9. The circuitry of claim 1 , in which the command processing circuitry is configured to access a translation information memory storing memory address translation information.

10. The circuitry of claim 9 , in which the memory address translation information comprises one or more hierarchies of page tables.

11. The circuitry of claim 9 , comprising a translation lookaside buffer to store information defining at least some memory address translations.

12. The circuitry of claim 9 , in which the memory management operations comprise one or more operations from the list consisting of:
an operation to invalidate an instance of translation information;
an operation to provide information to allow the loading, into the translation information memory, memory address translation information defining a given memory address translation specified by the operation and to return an indication of completion of the loading into the translation information memory;
an operation to terminate or resume a memory address translation operation after that memory address translation operation has been stalled.

13. The circuitry of claim 1 , in which the set of one or more command queues comprises a set of two or more command queues.

14. The circuitry of claim 13 , in which the set of one or more command queues comprises one or more enhanced command queues each associated with management by a respective operating system, hypervisor or other software, and in which the circuitry is responsive to one or more further command queues accessible by management software relating to any operating system, hypervisor or other software.

15. A method comprising:
storing data defining a set of one or more command queues each associated with a respective memory address space, each command queue defining successive commands for execution from a queue head to a queue tail, the commands being selected from a set of commands comprising synchronization commands and one or more other commands defining memory management operations for a given memory address space, in which completion of a synchronization command is dependent upon one or more completion criteria indicating that all commands from any of the one or more command queues which are earlier than the synchronization command in an execution order have completed;
executing the commands;
maintaining a linked list of entries having a list order, each entry defining a respective one of the one or more command queues, in which the command processing circuitry is configured to execute commands at the queue head of the one or more command queues, the one or more command queues being defined by prevailing entries of the linked list of entries for execution in the list order; and
for a current occupancy of the linked list at a given stage of executing commands from command queues defined by entries of the linked list:
executing a first synchronization command earliest in the list order;
detecting, within the given current occupancy of the linked list at the given stage, any further synchronization commands at the queue head of the one or more command queues which are defined by entries of the linked list later in the list order; and
applying, for any such further synchronization commands, the completion criteria of the synchronization command at the head of a given command queue, the given command queue being defined by an entry of the linked list earliest in the list order so as to treat the further synchronization commands as having been completed.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Geng Guanghui
• Swaine Andrew Brookfield

Classifications

• G06F13/225 Primary

  with priority control · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F12/1491

  in a hierarchical protection system, e.g. privilege levels, memory rings · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title