Writing beyond a pointer

Patent metadata

Field	Value
Publication number	US-12099445-B2
Application number	US-202318320407-A
Country	US
Kind code	B2
Filing date	May 19, 2023
Priority date	May 27, 2022
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

Data processing apparatuses and methods of data processing are disclosed wherein a processing element maintains a buffer in the memory in support of the data processing it performs. A write pointer indicates a current write location in the buffer. A cache holds copies of the data which are subject to the data processing operations and allocations into the cache from the memory and write-backs from the cache to the memory are performed in cache line units of data. When the processing element performs a data write to the buffer at a location determined by the write pointer, the processor updates the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.

First claim

What is claimed is:

1. A data processing apparatus comprising:
processing circuitry configured to perform data processing operations;
a memory configured to store data which is subject to the data processing operations, wherein as part of the data processing operations, the processing circuitry is configured to maintain a buffer in the memory;
a register configured to hold a write pointer indicative of a current write location in the buffer; and
a cache configured to cache copies of the data which are subject to the data processing operations by the processing circuitry, wherein the copies of the data are stored in cache lines, wherein the cache is configured to perform allocation into the cache from the memory and write-back from the cache to the memory in cache line units of data, and
wherein the processing circuitry is configured, when the processing circuitry performs a data write to the buffer at a location determined by the write pointer, to update the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.

2. The data processing apparatus as claimed in claim 1 , further comprising a storage associated with the cache and configured to store indicator values associated with each cache line of the cache, wherein respective bits of an indicator value indicate which data items of a cache line are signalled to have the predetermined value.

3. The data processing apparatus as claimed in claim 2 , wherein signalling that the further locations in the progression direction in the buffer between the location indicated by the write pointer and the boundary location are to be written with the predetermined value comprises setting bits of at least one indicator value associated with at least one cache line associated with the further locations.

4. The data processing apparatus as claimed in claim 1 , wherein the processing circuitry is configured to maintain the buffer in the memory in a last-in-first-out manner, wherein a pushed data item entry added to the buffer is written at the location determined by the write pointer, wherein removal of a popped data item from the buffer comprises popping the popped data item from a pop location adjacent to the location determined by the write pointer in an opposite direction to the progression direction, and wherein the pop location is signalled to be written with the predetermined value.

5. The data processing apparatus as claimed in claim 4 , wherein the removal of the popped data item from the buffer comprises un-setting the bits of the at least one indicator value associated with the at least one cache line associated with the further locations and un-setting a bit of an indicator value associated with the pop location.

6. The data processing apparatus as claimed in claim 1 , wherein the boundary location corresponds to a cache line extremity.

7. The data processing apparatus as claimed in claim 6 , wherein the cache line extremity corresponds to one of: a cache line end; or a cache line start.

8. The data processing apparatus as claimed in claim 1 , wherein the processing circuitry is configured to update the write pointer in an ascending direction corresponding to an ascending progression direction of data writes in the buffer.

9. The data processing apparatus as claimed in claim 1 , wherein the processing circuitry is configured to update the write pointer in a descending direction corresponding to a descending progression direction of data writes in the buffer.

10. The data processing apparatus as claimed in claim 1 , wherein the data processing operations performed by the processing circuitry comprise data sampling and wherein the buffer in the memory is a sample data buffer.

11. The data processing apparatus as claimed in claim 1 , wherein the data processing operations performed by the processing circuitry comprise generation of program-flow trace data and wherein the buffer in the memory is a trace buffer.

12. The data processing apparatus as claimed in claim 1 , wherein the data processing operations performed by the processing circuitry comprise execution of branch instructions and return instructions, and wherein the buffer in the memory is a hardware shadow stack.

13. The data processing apparatus as claimed in claim 1 , wherein the buffer in the memory is a software stack, wherein the data processing operations performed by the processing circuitry comprise pushing data onto the software stack and popping data from the software stack.

14. The data processing apparatus as claimed in claim 1 , wherein the boundary location is the extremity of the cache line in which the data value at the location is stored temporarily in the cache.

15. The data processing apparatus as claimed in claim 1 , wherein the boundary location is the extremity of a further cache line which is not the cache line in which the data value at the location is stored temporarily in the cache, and wherein a contiguous block of data between the location determined by the write pointer at which the processing circuitry performs the data write to the buffer and the extremity of the further cache line is caused to be written with the predetermined value.

16. The data processing apparatus as claimed in claim 15 , wherein the boundary location corresponds to a memory page boundary.

17. The data processing apparatus as claimed in claim 16 , wherein the processing circuitry is configured to maintain the buffer in a wrap-around manner, wherein the buffer is arranged to cover a predetermined range of memory locations and when a write has reached an extremity of the predetermined range of memory locations in the progression direction of data writes in the buffer the processing circuitry performs a next data write to the buffer at an opposite extremity of the predetermined range of memory locations, and wherein the contiguous block of data has a predetermined maximum size.

18. The data processing apparatus as claimed in claim 1 , further comprising at least one control register configured to hold a control value, wherein the processing circuitry is configured to signal the predetermined value to be written to the further locations in the procession direction in the buffer between the location indicated by the write pointer and the boundary location is further dependent on the control value.

19. The data processing apparatus as claimed in claim 1 , wherein access to data stored in the memory is dependent on configuration data stored in at least one access control table stored in the memory, wherein the configuration data defines for each location in the memory characteristics of the access, and wherein the processing circuitry is configured to signal the predetermined value to be written to the further locations in the progression direction in the buffer between the location indicated by the write pointer and the boundary location is further dependent on the configuration data corresponding to the location indicated by the write pointer.

20. A method of data processing comprising:
performing data processing operations;
storing data which is subject to the data processing operations in a memory, wherein the data processing operations comprise maintaining a buffer in the memory;
holding in a register a write pointer indicative of a current write location in the buffer; and
caching i

Assignees

• Advanced Risc Mach Ltd

Inventors

• Williams Michael John
• Horley John Michael

Classifications

• G06F12/0888

  using selective caching, e.g. bypass · CPC title

• G06F12/0804 Primary

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F11/36

  Prevention of errors by analysis, debugging or testing of software · CPC title

• G06F9/38

  Concurrent instruction execution, e.g. pipeline or look ahead · CPC title

• G06F9/30

  Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22) · CPC title