Memory controller, information processing apparatus, and information processing method

Patent metadata

Field	Value
Publication number	US-12099413-B2
Application number	US-202318101875-A
Country	US
Kind code	B2
Filing date	Jan 26, 2023
Priority date	Mar 30, 2022
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A memory controller includes a request pipeline and a retry control circuit. The request pipeline receives an input of a request to a memory output from a processor core, stores the request, and causes the memory to process the request in order of storage. The retry control circuit stops a new request input to the request pipeline when an error occurs in the memory, and re-inputs, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline.

First claim

What is claimed is:

1. A memory controller comprising:
a request pipeline that receives an input of a request to a memory output from a processor core, stores the request, and causes the memory to process the request in order of storage;
a retry control circuit that stops a new request input to the request pipeline when an error occurs in the memory, and re-inputs, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline;
a request queue that stores a plurality of the requests; and
a busy check circuit that obtains the request that may be processed by the memory from the request queue, deletes the request from the request queue, and inputs the obtained request to the request pipeline.

2. The memory controller according to claim 1 , wherein the retry control circuit puts the memory, which has stopped accepting the request due to the occurrence of the error, into a state of being enabled to accept the request, and re-inputs the requests to be retried.

3. The memory controller according to claim 1 , wherein the retry control circuit resumes a new request input to the request pipeline when a retry of all of the requests to be retried is complete.

4. The memory controller according to claim 1 , wherein
the request pipeline assigns, to the stored request, a sequence number that indicates a number of times that the re-input has been executed and a complete flag that indicates processing completion, and
the retry control circuit generates a retry number that indicates a number of times of execution of the re-input, a stop enable signal that permits a stoppage of shift operation of the request pipeline, and a stop number for determining the request to be retried, and controls discard of the request stored in the request pipeline, the shift operation of the request pipeline, and the re-input on a basis of the retry number, the stop enable signal, the stop number, the sequence number, and the complete flag.

5. An information processing apparatus comprising:
a memory; and
a processor including a core and a memory controller;
wherein the memory controller includes:
a request pipeline that receives an input of a request to a memory output from a processor core, stores the request, and causes the memory to process the request in order of storage;
a retry control circuit that stops a new request input to the request pipeline when an error occurs in the memory, and re-inputs, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline;
a request queue that stores a plurality of the requests; and
a busy check circuit that obtains the request that may be processed by the memory from the request queue, deletes the request from the request queue, and inputs the obtained request to the request pipeline.

6. An information processing method performed by a computer, the method comprising:
inputting requests to a memory output from a processor core into a request queue that stores a plurality of requests;
obtaining a request that may be processed by the memory from the request queue;
deleting the request from the request queue, and inputting the obtained request to a request pipeline;
storing the request in the request pipeline;
causing the memory to process the request in order of storage;
stopping a new request input to the request pipeline when an error occurs in the memory, and
re-inputting, to the request pipeline, requests to be retried that includes the request in which the error has occurred and a subsequent request stored in the request pipeline.

Assignees

• Fujitsu Ltd

Inventors

• Kitamura Yasuhiro

Classifications

• G06F11/141

  for bus or memory accesses · CPC title

• G06F11/0772

  Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers · CPC title

• G06F9/30079

  Pipeline control instructions, e.g. multicycle NOP · CPC title

• G06F13/1621

  by maintaining request order · CPC title

• G06F11/1405 Primary

  at machine instruction level · CPC title