TFT array substrate and display panel

Patent metadata

Field	Value
Publication number	US-12096664-B2
Application number	US-201917262752-A
Country	US
Kind code	B2
Filing date	Nov 18, 2019
Priority date	Aug 12, 2019
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

The disclosure provides a thin film transistor (TFT) array substrate provided with a display area and a bending area, including a substrate layer and a functional layer disposed on the substrate layer, wherein the functional layer includes a plurality of insulating layers and a plurality of metal layers. In the bending area, the metal layers include a first metal layer, a second metal layer, and a second gate layer. The first metal layer is disposed on a side end of a filling layer and connects to the second gate layer by a through hole. The second metal layer is disposed on an insulating layer on an outer side of the first metal layer.

First claim

What is claimed is:

1. A thin film transistor (TFT) array substrate provided with a display area and a bending area, comprising a substrate layer and a functional layer disposed on the substrate layer, wherein the functional layer comprises a plurality of insulating layers and a plurality of metal layers;
wherein a deep hole is defined in the functional layer in the bending area, a filling layer is disposed in the deep hole, and a side end at top of the filling layer protrudes from a periphery of the deep hole;
wherein in the bending area, the metal layers comprise a first metal layer, a second metal layer, and a second gate layer, and the insulating layers of the functional layer are disposed between the second gate layer, the first metal layer, and the second metal layer; and
wherein the first metal layer is disposed on the side end of the filling layer and is connected to the second gate layer by a through hole, and the second metal layer is disposed on an insulating layer on an outer side of the first metal layer,
wherein the metal layers in the bending area comprise a first gate layer, a gate insulating layer is disposed between the first gate layer and the second gate layer, and the insulating layers disposed between the second gate layer and the first metal layer constitute an interlayer dielectric layer,
wherein the second metal layer is connected to the first gate layer by the through hole,
wherein the first metal layer is not connected to the second metal layer.

2. The TFT array substrate of claim 1 , wherein the insulating layers disposed between the first metal layer and the second metal layer constitute a first planarization layer, and the side end of the filling layer covers a portion of the interlayer dielectric layer.

3. The TFT array substrate of claim 1 , wherein a transfer metal layer is disposed between the second metal layer and the first gate layer, the second metal layer is connected to the transfer metal layer by the through hole, and the transfer metal layer is connected to the first gate layer by the through hole.

4. The TFT array substrate of claim 1 , wherein the functional layer in the bending area comprises a buffer layer, the buffer layer is disposed on the substrate layer, and the filling layer penetrates the buffer layer and enters the substrate layer.

5. The TFT array substrate of claim 4 , wherein the substrate layer comprises a polyimide layer and a barrier layer disposed on the polyimide layer, and a bottom of the filling layer penetrates the barrier layer and reaches a surface of the polyimide layer.

6. The TFT array substrate of claim 1 , wherein in the bending area, an insulating layer between the first metal layer and the second metal layer is a first planarization layer, and a second planarization layer covers the second metal layer.

7. A display panel, comprising the TFT array substrate of claim 1 .

8. The display panel of claim 7 , wherein the display panel is a flexible active-matrix organic light-emitting diode display panel.

Assignees

• Wuhan China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Ming Xing
• Cao Zhongtao

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10K2102/311

  Flexible OLED · CPC title

• H10K77/111

  Flexible substrates · CPC title