Component carrier with stack-stack connection for connecting components

Patent metadata

Field	Value
Publication number	US-12096555-B2
Application number	US-202217655162-A
Country	US
Kind code	B2
Filing date	Mar 16, 2022
Priority date	Mar 16, 2022
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

A component carrier includes a first stack with an electrically insulating layer structure and an electrically conductive layer structure with a first density of trace structures and a second density of first connection structures, a second stack with a second electrically insulating layer structure and a second electrically conductive layer structure with a third density of second trace structures and a fourth density of second connection structures. A first component is applied to the first stack and a second component is embedded in the second stack. The first connection structures are respectively connected to the second connection structures. The first density of first trace structures is lower than the third density of second trace structures. The first stack and the second stack are connected with each other by the first connection structures and by the second connection structures. The first component is connected to the second component.

First claim

The invention claimed is:

1. A component carrier, comprising:
a first stack comprising at least one first electrically insulating layer structure and a plurality of first electrically conductive layer structures at least part of which having a first density of first trace structures and a second density of first connection structures,
wherein the first trace structures and the first connection structures are connected;
a second stack comprising at least one second electrically insulating layer structure and electrically conductive layer structures having a third density of second trace structures and a fourth density of second connection structures,
wherein the second trace structures and the second connection structures are connected;
at least one first component electrically coupled to the first stack, wherein the at least one first component comprises at least one component embedded in the first stack and/or at least one component surface mounted on the first stack; and
at least one second component embedded in the second stack;
wherein the first connection structures are respectively connected to the second connection structures;
wherein the first density of first trace structures is lower than the third density of second trace structures;
wherein the first stack and the second stack are connected with each other by the first connection structures of the first stack and by the second connection structures of the second stack;
wherein the at least one first component is connected to the at least one second component; and
wherein the second stack is surface-mounted on the first stack.

2. The component carrier according to claim 1 , wherein the at least one second component is encapsulated by an electrically insulating encapsulant.

3. The component carrier according to claim 1 , wherein the first electrically conductive layer structures comprise a lower density stack coupling region and a higher density stack coupling region, wherein the higher density stack coupling region has the first density of first trace structures and has the second density of first connection structures.

4. The component carrier according to claim 3 , wherein a line pitch of the lower density stack coupling region is in a range from 30 μm to 120 μm.

5. The component carrier according to claim 3 , wherein a line pitch of the higher density stack coupling region is in a range from 2 μm to below 30 μm.

6. The component carrier according to claim 1 , wherein a line pitch of the second electrically conductive layer structures is in a range from 0.4 μm to 10 μm.

7. The component carrier according to claim 1 , wherein at least one of the at least one first component and the at least one second component comprises at least one of the group comprising a processor chip, a memory chip, a wafer level package, a bridge die, stacked dies, and an interposer, in particular an active interposer.

8. The component carrier according to claim 1 , wherein at least a portion of the second connection structures is located at a bottom main surface of the second stack.

9. The component carrier according to claim 1 , wherein at least a portion of the second connection structures is located at a top main surface of the second stack.

10. The component carrier according to claim 1 , wherein the second density of first connection structures and the fourth density of second connection structures differ from each other by not more than +/−20%.

11. The component carrier according to claim 1 , wherein the second connection structures are arranged at a main surface of the second stack facing the first stack.

12. The component carrier according to claim 1 , further comprising:
a third stack comprising a plurality of other third electrically conductive layer structures having a fifth density of fifth trace structures and a sixth density of sixth connection structures, and at least one third component embedded in the third stack;
wherein the second density of first connection structures and the sixth density of third connection structures differ from each other by not more than +/−20%;
wherein the first density of first trace structures is lower than the fifth density of third trace structures;
wherein the first stack and the third stack are connected with each other by the first connection structures of the first stack and by the third connection structures of the third stack; and
wherein the at least one first component and/or the at least one second component is or are connected to the at least one third component.

13. The component carrier according to claim 1 , comprising at least one of the following features:
wherein the second stack is configured as chiplet, as a package accommodated at least partially in a cavity, as a package comprising vertically stacked semiconductor chips, and/or comprises a chiplet mounted on the second stack;
wherein a central portion of the first stack comprises a core, a coreless build-up, and/or a multilayer build-up.

14. A method of manufacturing a component carrier, the method comprising:
providing a first stack comprising an electrically insulating layer structure and an electrically conductive layer structure at least part of which having a first density of first trace structures and a second density of first connection structures, wherein the first trace structures and the first connection structures are connected;
providing a second stack comprising a second electrically insulating layer structure and a second electrically conductive layer structure having a third density of second trace structures and a fourth density of second connection structures,
wherein the second trace structures and the second connection structures are connected;
coupling at least one first component to the first stack, wherein the at least one first component comprises at least one component embedded in the first stack and/or at least one component surface mounted on the first stack;
embedding at least one second component in the second stack;
providing the first stack and the second stack so that the second density of first connection structures and the fourth density of second connection structures differ from each other by not more than +/−20%;
providing the first stack and the second stack so that the first density of first trace structures is lower than the third density of second trace structures;
connecting the first stack and the second stack with each other by the first connection structures of the first stack and by the second connection structures of the second stack; and
connecting the at least one first component to the at least one second component,
wherein the second stack is surface mounted on the first stack.

Assignees

• At & S Austria Tech & Systemtechnik Ag
• At&S Austria Tech & Systemtechnik Ag

Inventors

• Leitgeb Markus
• Grober Gernot

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/60 Primary

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H05K1/183

  associated with components mounted in and supported by recessed areas of the PCBs · CPC title