DML driver

Patent metadata

Field	Value
Publication number	US-12095225-B2
Application number	US-202017431071-A
Country	US
Kind code	B2
Filing date	Mar 12, 2020
Priority date	Mar 26, 2019
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

The DML driver includes: a post driver which supplies a driving current to the LD; and a pre-driver which drives the post driver in response to a modulated signal. The pre-driver has a transistor, a peaking inductor, a peaking inductor, a group delay inhibition inductor, and a peaking capacitor.

First claim

The invention claimed is:

1. A DML driver comprising:
a post driver configured to supply a driving current to a laser diode; and
a pre-driver configured to drive the post driver in response to an inputted modulated signal, the pre-driver including:
a first transistor, wherein the inputted modulated signal is configured to be input into a gate of the first transistor or a base of the first transistor;
a first resistor, wherein a first end of the first resistor is connected to a first power supply voltage;
a first inductor, wherein a first end of the first inductor is connected to a second end of the first resistor, wherein a second end of the first inductor is connected to a drain of the first transistor or a collector of the first transistor;
a second inductor, wherein a first end of the second inductor is connected to the drain of the first transistor or the collector of the first transistor, wherein a second end of the second inductor is connected to an input terminal of the post driver;
a third inductor, wherein a first end of the third inductor is connected to a source of the first transistor or an emitter of the first transistor, wherein a second end of the third inductor is connected to a second power supply voltage; and
a capacitor, wherein a first end of the capacitor is connected to the source of the first transistor or the emitter of the first transistor, wherein a second end of the capacitor is connected to the second power supply voltage.

2. The DML driver according to claim 1 , wherein the pre-driver further includes a second resistor between the source of the first transistor or the emitter of the first transistor and the first end of the third inductor as well as the first end of the capacitor.

3. The DML driver according to claim 1 , wherein the pre-driver further includes a second resistor between the source of the first transistor and the second end of the third inductor or between the emitter of the first transistor and the second end of the third inductor.

4. The DML driver according to claim 1 , wherein the pre-driver further includes a second transistor between a connection point and the drain of the first transistor or between the connection point and the collector of the first transistor, wherein the connection point is of the first inductor and the second inductor, wherein a bias voltage is configured to be input to the a gate of the second transistor or a base of the second transistor, wherein a drain of the second transistor or a collector of the second transistor is connected to the connection point, and wherein a source of the second transistor or an emitter of the second transistor is connected to the drain of the first transistor or the collector of the first transistor.

5. A method comprising:
supplying, by a post driver of a DML driver, a driving current to a laser diode; and
driving, by a pre-driver of the DML driver, the post driver in response to an inputted modulated signal, the pre-driver including:
a first transistor, wherein the inputted modulated signal is input into a gate of the first transistor or a base of the first transistor;
a first resistor, wherein a first end of the first resistor is connected to a first power supply voltage;
a first inductor, wherein a first end of the first inductor is connected to a second end of the first resistor, wherein a second end of the first inductor is connected to a drain of the first transistor or a collector of the first transistor;
a second inductor, wherein a first end of the second inductor is connected to the drain of the first transistor or the collector of the first transistor, wherein a second end of the second inductor is connected to an input terminal of the post driver;
a third inductor, wherein a first end of the third inductor is connected to a source of the first transistor or an emitter of the first transistor, wherein a second end of the third inductor is connected to a second power supply voltage; and
a capacitor, wherein a first end of the capacitor is connected to the source of the first transistor or the emitter of the first transistor, wherein a second end of the capacitor is connected to the second power supply voltage.

6. The method according to claim 5 , wherein the pre-driver further includes a second resistor between the source of the first transistor or the emitter of the first transistor and the first end of the third inductor as well as the first end of the capacitor.

7. The method according to claim 5 , wherein the pre-driver further includes a second resistor between the source of the first transistor and the second end of the third inductor or between the emitter of the first transistor and the second end of the third inductor.

8. The method according to claim 5 , wherein the pre-driver further includes a second transistor between a connection point and the drain of the first transistor or between the connection point and the collector of the first transistor, wherein the connection point is of the first inductor and the second inductor, wherein a bias voltage is configured to be input to the a gate of the second transistor or a base of the second transistor, wherein a drain of the second transistor or a collector of the second transistor is connected to the connection point, and wherein a source of the second transistor or an emitter of the second transistor is connected to the drain of the first transistor or the collector of the first transistor.

Assignees

• Nippon Telegraph & Telephone

Inventors

• Kishi Toshiki
• Nagatani Munehiko
• Nosaka Hideyuki

Classifications

• H01S5/06226

  Modulation at ultra-high frequencies · CPC title

• H01S5/06213

  Amplitude modulation · CPC title

• H03F1/48

  of aperiodic amplifiers · CPC title

• H04B10/516

  Details of coding or modulation · CPC title

• H03F3/68

  Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)} · CPC title