Semiconductor device and method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-12094959-B2
Application number	US-201917601433-A
Country	US
Kind code	B2
Filing date	May 29, 2019
Priority date	May 29, 2019
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

Provided is a technology that suppresses the removal of collector layers in the planarization process while suppressing the snapback phenomenon. A semiconductor device related to a technology disclosed in the present specification includes a drain layer of first conductivity type in a part of a lower surface a drift layer, a plurality of collector layers of second conductivity type in parts of the lower surface of the drift layer, and a dummy layer of the first conductivity type interposed between the plurality of collector layers in parts of the lower surface of the drift layer, in which a width of the dummy layer 3 in a first direction, which is the direction in which the dummy layer is interposed between the plurality of collector layers, is narrower than a width of the drain layer in the first direction.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a drift layer of first conductivity type;
a base layer of second conductivity type in a surface layer on an upper surface of the drift layer;
a source layer of the first conductivity type in a surface layer of the base layer;
a gate insulating film in contact with the base layer interposed between the source layer and the drift layer;
a gate electrode in contact with the gate insulating film;
an interlayer insulating film covering the gate electrode;
an emitter electrode covering an upper surface of the source layer and the interlayer insulating film;
a drain layer of the first conductivity type in a part of a lower surface of the drift layer;
a plurality of collector layers of the second conductivity type in parts of the lower surface of the drift layer;
a dummy layer of the first conductivity type interposed between the plurality of collector layers in parts of the lower surface of the drift layer; and
a collector electrode that is brought into ohmic contact with the collector layers via a first silicide layer of the second conductivity type, wherein
a width of the dummy layer in a first direction, which is a direction in which the dummy layer is interposed between the plurality of collector layers, is narrower than a width of the drain layer in the first direction.

2. The semiconductor device according to claim 1 , wherein
the width of the dummy layer in the first direction is narrower than a width of the collector layers in the first direction.

3. The semiconductor device according to claim 1 , further comprising
a first separation layer of the second conductivity type between the dummy layer and the first silicide layer.

4. The semiconductor device according to claim 1 , wherein
the dummy layer is not brought into ohmic contact with the collector electrode.

5. The semiconductor device according to claim 1 , further comprising
an insulating layer between the dummy layer and the collector electrode.

6. The semiconductor device according to claim 1 , further comprising
a second separation layer of the second conductivity type between the dummy layer and the drift layer.

7. The semiconductor device according to claim 1 , further comprising
an impurity layer of the first conductivity type between the dummy layer and the drift layer, having an impurity concentration lower than that of the dummy layer.

8. The semiconductor device according to claim 1 , wherein
the drift layer is made of SiC.

9. A method of manufacturing a semiconductor device comprising:
forming a plurality of trenches on an upper surface of a semiconductor substrate of first conductivity type;
depositing an impurity layer of second conductivity type on the upper surface of the semiconductor substrate including inside of the plurality of trenches by epitaxial growth of the second conductivity type;
removing the impurity layer formed in the region other than the inside of the trenches, wherein
the impurity layers inside of the trenches represent collector layers, a layer of the first conductivity type interposed between the plurality of trenches represent a dummy layer, and a layer of the first conductivity type on outside of the trenches represent a drain layer;
forming a drift layer of the first conductivity type on an upper surface of the semiconductor substrate by epitaxial growth of the first conductivity type; and
removing a lower surface of the semiconductor substrate until the collector layers are exposed, wherein
a width of the dummy layer in a first direction, which is a direction in which the dummy layer is interposed between the plurality of collector layers, is narrower than a width of the drain layer in the first direction.

10. The method of manufacturing the semiconductor device according to claim 9 , further comprising:
forming a base layer of the second conductivity type in a surface layer on an upper surface of the drift layer;
forming a source layer of the first conductivity type in a surface layer of the base layer;
forming a gate insulating film interposed between the source layer and the drift layer and in contact with the base layer;
forming a gate electrode in contact with the gate insulating film;
forming an interlayer insulating film covering the gate electrode;
forming an emitter electrode covering an upper surface of the source layer and the interlayer insulating film; and
forming a collector electrode that is brought into ohmic contact with the collector layers.

11. The method of manufacturing the semiconductor device according to claim 9 , wherein
the width of the dummy layer in the first direction is narrower than a width of the collector layers in the first direction.

12. The method of manufacturing the semiconductor device according to claim 9 , wherein
the drift layer is made of SiC.

13. The semiconductor device according to claim 1 , wherein
the first silicide layer of the second conductivity type is on a lower surface of the plurality of collector layers and the dummy layer, and the semiconductor device further comprises:
a second silicide layer of the first conductivity type on a lower surface of the drain layer and interposed between portions of the first silicide layer in the first direction.

14. The semiconductor device according to claim 13 , wherein
the first silicide layer and the second silicide layer are on an upper surface of the collector electrode.

15. The semiconductor device according to claim 3 , wherein
the first separation layer contacts a lower surface of the dummy layer and an upper surface of the first silicide layer.

16. The semiconductor device according to claim 6 , wherein
the second separation layer contacts an upper surface of the dummy layer and a lower surface of the drift layer.

Assignees

• Mitsubishi Electric Corp

Inventors

• Konishi Kazuya
• Tarui Yoichiro
• Niwa Hiroki
• Okabe Hiroaki
• Watanabe Hiroshi

Classifications

• H10D12/032

  of vertical IGBTs · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title