Sensor module, method for manufacturing same, and display panel

Patent metadata

Field	Value
Publication number	US-12094890-B2
Application number	US-202017252274-A
Country	US
Kind code	B2
Filing date	Oct 22, 2020
Priority date	Sep 4, 2020
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

The present application provides a sensor module, a method for manufacturing the sensor module, and a display panel. The sensor module is integrated by a light-sensitive PN junction and a bottom-gate thin film transistor, a limitation of an integration of top-gate thin film transistor photosensitive sensor is prevented, and a problem of increased thickness and development cost in an integration of a photosensitive sensor on a bottom surface and the display panel is solved.

First claim

What is claimed is:

1. A sensor module, comprising:
a substrate, wherein the substrate comprises a first surface and a second surface opposite to each other;
a gate electrode layer, wherein the gate electrode layer partly covers the first surface, the gate electrode layer comprises a first portion and a second portion, the first portion comprises a connecting portion and at least two sub gate electrode layers, spaces are defined between the sub gate electrode layers, and an end of the sub gate electrode layers is connected to the connecting portion;
a first semiconductor layer, wherein the first semiconductor layer is disposed on a side of the first portion away from the first surface and insets into the spaces;
a first source and drain electrode layer, wherein the first source and drain electrode layer is disposed on a side of the first semiconductor layer away from the gate electrode layer, and the first portion, the first semiconductor layer, and the first source and drain electrode layer are combined to form a light-sensitive PN junction; and
a thin film transistor, wherein the thin film transistor and the light-sensitive PN junction are disposed on the first surface and adjacent to each other, and the second portion is a gate electrode of the thin film transistor;
wherein the thin film transistor further comprises a gate electrode insulating layer, a second semiconductor layer, and a second source and drain electrode layer, the gate electrode insulating layer is disposed on a side of the second portion away from the first surface and extends to the first surface, the second semiconductor layer partly covers a side of the gate electrode insulating layer away from the second portion, the second source and drain electrode layer partly covers a side of the second semiconductor layer away from the gate electrode insulating layer and extends to the gate electrode insulating layer, and a first through hole is defined in the second source and drain electrode layer covering the second semiconductor layer; and
wherein the sensor module further comprises a passivation layer and a pixel electrode layer, the passivation layer covers the light-sensitive PN junction and the thin film transistor, and extends to the first surface.

2. The sensor module of claim 1 , wherein the first source and drain electrode layer comprises a first P-type material layer and a first electrode material layer, the first P-type material layer is disposed on a side near the first semiconductor layer, the first electrode material layer is disposed on a side away from the first semiconductor layer, the first P-type material layer is made of one or a group selected from molybdenum oxide and tin oxide, and the first electrode material layer is made of metal or metal oxide.

3. The sensor module of claim 2 , wherein a thickness of the first source and drain electrode layer ranges from 300 Å to 800 Å.

4. The sensor module of claim 1 , wherein the first source and drain electrode layer is disposed in an orthographic projection region of the first semiconductor layer projected on the first surface, and a covered area of the first source and drain electrode layer is less than a covered area of the first semiconductor layer.

5. The sensor module of claim 1 , wherein the gate electrode layer is made of metal or metal alloy, and a thickness of the gate electrode layer ranges from 3000 Å to 8000 Å.

6. The sensor module of claim 1 , wherein the first semiconductor layer is made of transparent metal oxide, and a thickness of the first semiconductor layer ranges from 300 Å to 800 Å.

7. The sensor module of claim 1 , wherein the second source and drain electrode layer comprises a second P-type material layer and a second electrode material layer, the second P-type material layer is disposed on a side near the second semiconductor layer, and the second electrode material layer is disposed on a side away from the second semiconductor layer.

8. The sensor module of claim 1 , wherein the passivation layer is connected to the second semiconductor layer by the first through hole, a second through hole is defined in the passivation layer, the pixel electrode layer partly covers a side of the passivation layer away from the first surface, and is connected to the second source and drain electrode layer by the second through hole.

9. A display panel, comprising a sensor module, wherein the sensor module comprises:
a substrate, wherein the substrate comprises a first surface and a second surface opposite to each other;
a gate electrode layer, wherein the gate electrode layer partly covers the first surface, the gate electrode layer comprises a first portion and a second portion, the first portion comprises a connecting portion and at least two sub gate electrode layers, spaces are defined between the sub gate electrode layers, and an end of the sub gate electrode layers is connected to the connecting portion;
a first semiconductor layer, wherein the first semiconductor layer is disposed on a side of the first portion away from the first surface and insets into the spaces;
a first source and drain electrode layer, wherein the first source and drain electrode layer is disposed on a side of the first semiconductor layer away from the gate electrode layer, and the first portion, the first semiconductor layer, and the first source and drain electrode layer are combined to form a light-sensitive PN junction; and
a thin film transistor, wherein the thin film transistor and the light-sensitive PN junction are disposed on the first surface and adjacent to each other, and the second portion is a gate electrode of the thin film transistor;
wherein the thin film transistor further comprises a gate electrode insulating layer, a second semiconductor layer, and a second source and drain electrode layer, the gate electrode insulating layer is disposed on a side of the second portion away from the first surface and extends to the first surface, the second semiconductor layer partly covers a side of the gate electrode insulating layer away from the second portion, the second source and drain electrode layer partly covers a side of the second semiconductor layer away from the gate electrode insulating layer and extends to the gate electrode insulating layer, and a first through hole is defined in the second source and drain electrode layer covering the second semiconductor layer; and
wherein the sensor module further comprises a passivation layer and a pixel electrode layer, the passivation layer covers the light-sensitive PN junction and the thin film transistor, and extends to the first surface.

10. The display panel of claim 9 , wherein the first source and drain electrode layer comprises a first P-type material layer and a first electrode material layer, the first P-type material layer is disposed on a side near the first semiconductor layer, the first electrode material layer is disposed on a side away from the first semiconductor layer, the first P-type material layer is made of one or a group selected from molybdenum oxide and tin oxide, and the first electrode material layer is made of metal or metal oxide.

11. The display panel of claim 10 , wherein a thickness of the first source and drain electrode layer ranges from 300 Å to 800 Å.

12. The display panel of claim 9 , wherein the first source and drain electrode layer is disposed in an orthographic projection region of the first semiconductor layer projected on the first surface, and a covered area of the first source and drain electrode layer is less than a covered area of the first semiconductor layer.

13. The display panel of claim 9 , wherein the gate electrode layer is made o

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Li Jinming

Classifications

• H10F39/016

  of thin-film-based image sensors · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/80373

  characterised by the gate of the transistor · CPC title

• H10F39/103 Primary

  the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors · CPC title