Memory device and computing method thereof

Patent metadata

Field	Value
Publication number	US-12094564-B2
Application number	US-202217817701-A
Country	US
Kind code	B2
Filing date	Aug 5, 2022
Priority date	Aug 5, 2022
Publication date	Sep 17, 2024
Grant date	Sep 17, 2024

Abstract

The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients, the memory array including at least one memory sub-array, the at least one memory sub-array including: a plurality of memory cells, a plurality of first signal lines, a plurality of second signal lines and a plurality of third signal lines coupled to the memory cells; and
at least one calculation unit, coupled to the at least one memory sub-array,
wherein,
the plurality of memory cells receive the plurality of input values via the plurality of second signal lines and the plurality of third signal lines, the plurality of memory cells generate a plurality of source currents, the plurality of source currents flowing through the plurality of first signal lines to generate a plurality of common source currents, the plurality of common source currents flowing into the at least one calculation unit, a first part of the plurality of memory cells generate a first part of the plurality of common source currents, a second part of the plurality of memory cells generate a second part of the plurality of common source currents;
the first part of the plurality of memory cells store a plurality of first part coefficients of the plurality of interact coefficients, and the second part of the plurality of memory cells store a plurality of second part coefficients of the plurality of interact coefficients, wherein the first part of the plurality of memory cells is electrically isolated from the second part of the plurality of memory cells based on a diagonal of the memory array; and
the at least one calculation unit calculates a first part of a local field energy of the model computation based on the first part of the plurality of common source currents, and calculates a second part of the local field energy of the model computation based on the second part of the plurality of common source currents.

2. The memory device according to claim 1 , wherein the at least one memory sub-array includes:
a first memory sub-array, the first memory sub-array being for storing a plurality of odd order interact coefficients, the first memory sub-array being on a diagonal position of the memory array;
a second memory sub-array, the second memory sub-array being for storing a plurality of even order interact coefficients, the second memory sub-array being on two sides of the memory array; and
a third memory sub-array, the third memory sub-array being turned off in normal operations.

3. The memory device according to claim 1 , wherein the at least one memory sub-array includes:
a plurality of first memory sub-arrays for storing a plurality of odd order interact coefficients, the plurality of first memory sub-arrays being on a diagonal position of the memory array;
a plurality of second memory sub-arrays for storing a plurality of even order interact coefficients, the plurality of second memory sub-arrays being on two sides of the memory array; and
a plurality of third memory sub-arrays, the plurality of third memory sub-arrays being turned off in normal operations;
the plurality of first memory sub-arrays, the plurality of second memory sub-arrays and the plurality of third memory sub-arrays form a plurality of groups;
in calculation, the plurality of groups independently calculate and one among the plurality of groups are selected to calculate the local field energy of the model computation, the plurality of input values are input into the selected group but not into the unselected groups.

4. The memory device according to claim 1 , wherein the at least one memory sub-array includes:
a plurality of first memory sub-arrays for storing a plurality of odd order interact coefficients, the plurality of first memory sub-arrays being on a diagonal position of the memory array;
a plurality of second memory sub-arrays for storing a plurality of even order interact coefficients, the plurality of second memory sub-arrays being on two sides of the memory array; and
a plurality of third memory sub-arrays, the plurality of third memory sub-arrays being turned off in normal operations;
the plurality of first memory sub-arrays, the plurality of second memory sub-arrays and the plurality of third memory sub-arrays form a plurality of groups;
in calculation, the plurality of groups independently calculate;
wherein the memory device further includes a switch circuit coupled between the plurality of first signal lines and the plurality of groups;
the plurality of input values are input into all the plurality of groups;
the switch circuit select at least one among the plurality of groups to output the local field energy of the model computation.

5. The memory device according to claim 4 , wherein the memory device includes a plurality of calculation units coupled to the plurality of first signal lines,
the switch circuit selects two or more among the plurality of groups to output the local field energy of the model computation.

6. An operation method for a memory device, for processing a model computation, the model computation having a plurality of input values and a plurality of interact coefficients, the operation method including:
storing a plurality of first part coefficients of the plurality of interact coefficients in a first part of a plurality of memory cells of at least one memory sub-array of a memory array of the memory device, storing a plurality of second part coefficients of the plurality of interact coefficients in a second part of the plurality of memory cells of the at least one memory sub-array of the memory device, wherein the first part of the plurality of memory cells is electrically isolated from the second part of the plurality of memory cells based on a diagonal of the memory array;
inputting the plurality of input values into the plurality of memory cells, the plurality of memory cells generate a plurality of source currents, the plurality of source currents flowing through a plurality of first signal lines of the memory device to generate a plurality of common source currents, the first part of the plurality of memory cells generate a first part of the plurality of common source currents, the second part of the plurality of memory cells generate a second part of the plurality of common source currents; and
calculating a first part of a local field energy of the model computation based on the first part of the plurality of common source currents, and calculating a second part of the local field energy of the model computation based on the second part of the plurality of common source currents.

7. The operation method according to claim 6 , wherein
the at least one memory sub-array includes: a first memory sub-array, a second memory sub-array and a third memory sub-array,
wherein the operation method further includes:
storing a plurality of odd order interact coefficients in the first memory sub-array, the first memory sub-array being on a diagonal position of the memory array;
storing a plurality of even order interact coefficients in the second memory sub-array, the second memory sub-array being on two sides of the memory array; and
turned off the third memory sub-array in normal operations.

8. The operation method according to claim 6 , wherein
the at least one memory sub-array includes: a plurality of first memory sub-arrays, a plurality of second memory sub-arrays and a plurality of third memory sub-arrays;
wherein the operation method further includes:
storing a plurality of odd order interact coefficients in the plurality of first memory sub-arrays, the plurality of first memory sub-arrays being on a diagonal position of the memory array;
storing a plurality of even

Assignees

• Macronix Int Co Ltd

Inventors

• Wang Yun-Yuan
• Lu Cheng-Hsien
• Lee Dai-Ying
• Lee Ming-Hsiu
• Lee Feng-Min

Classifications

• G11C7/109

  Control signal input circuits · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C2207/002

  Isolation gates, i.e. gates coupling bit lines to the sense amplifier · CPC title

• G11C7/16

  Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters · CPC title